drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h- Extension
.h- Size
- 8822 bytes
- Lines
- 123
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vce_4_0_DEFAULT_HEADER
#define _vce_4_0_DEFAULT_HEADER
// addressBlock: vce0_vce_dec
#define mmVCE_STATUS_DEFAULT 0x00000000
#define mmVCE_VCPU_CNTL_DEFAULT 0x00200000
#define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET4_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE4_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET5_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE5_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET6_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE6_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET7_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE7_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_OFFSET8_DEFAULT 0x00000000
#define mmVCE_VCPU_CACHE_SIZE8_DEFAULT 0x00000000
#define mmVCE_SOFT_RESET_DEFAULT 0x00000001
#define mmVCE_RB_BASE_LO2_DEFAULT 0x00000000
#define mmVCE_RB_BASE_HI2_DEFAULT 0x00000000
#define mmVCE_RB_SIZE2_DEFAULT 0x00000000
#define mmVCE_RB_RPTR2_DEFAULT 0x00000000
#define mmVCE_RB_WPTR2_DEFAULT 0x00000000
#define mmVCE_RB_BASE_LO_DEFAULT 0x00000000
#define mmVCE_RB_BASE_HI_DEFAULT 0x00000000
#define mmVCE_RB_SIZE_DEFAULT 0x00000000
#define mmVCE_RB_RPTR_DEFAULT 0x00000000
#define mmVCE_RB_WPTR_DEFAULT 0x00000000
#define mmVCE_RB_ARB_CTRL_DEFAULT 0x00010000
#define mmVCE_CLOCK_GATING_A_DEFAULT 0x00000040
#define mmVCE_CLOCK_GATING_B_DEFAULT 0x01ef0100
#define mmVCE_RB_BASE_LO3_DEFAULT 0x00000000
#define mmVCE_RB_BASE_HI3_DEFAULT 0x00000000
#define mmVCE_RB_SIZE3_DEFAULT 0x00000000
#define mmVCE_RB_RPTR3_DEFAULT 0x00000000
#define mmVCE_RB_WPTR3_DEFAULT 0x00000000
#define mmVCE_SYS_INT_EN_DEFAULT 0x00000000
#define mmVCE_SYS_INT_ACK_DEFAULT 0x00000000
#define mmVCE_SYS_INT_STATUS_DEFAULT 0x00000000
// addressBlock: vce0_ctl_dec
#define mmVCE_UENC_CLOCK_GATING_DEFAULT 0xffc00040
#define mmVCE_UENC_REG_CLOCK_GATING_DEFAULT 0x000007ff
#define mmVCE_UENC_CLOCK_GATING_2_DEFAULT 0x00010000
// addressBlock: vce0_vce_sclk_dec
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_DEFAULT 0x00000000
#define mmVCE_LMI_CTRL2_DEFAULT 0x00000000
#define mmVCE_LMI_SWAP_CNTL3_DEFAULT 0x00000000
#define mmVCE_LMI_CTRL_DEFAULT 0x00104000
#define mmVCE_LMI_STATUS_DEFAULT 0x00003f7f
#define mmVCE_LMI_VM_CTRL_DEFAULT 0x00000000
#define mmVCE_LMI_SWAP_CNTL_DEFAULT 0x00000000
#define mmVCE_LMI_SWAP_CNTL1_DEFAULT 0x00000000
#define mmVCE_LMI_SWAP_CNTL2_DEFAULT 0x00000000
#define mmVCE_LMI_CACHE_CTRL_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_DEFAULT 0x00000000
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_DEFAULT 0x00000000
// addressBlock: vce0_mmsch_dec
#define mmVCE_MMSCH_VF_VMID_DEFAULT 0x00000000
#define mmVCE_MMSCH_VF_CTX_ADDR_LO_DEFAULT 0x00000000
#define mmVCE_MMSCH_VF_CTX_ADDR_HI_DEFAULT 0x00000000
#define mmVCE_MMSCH_VF_CTX_SIZE_DEFAULT 0x00000000
#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_DEFAULT 0x00000000Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.