drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h- Extension
.h- Size
- 18908 bytes
- Lines
- 209
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vce_4_0_OFFSET_HEADER
#define _vce_4_0_OFFSET_HEADER
// addressBlock: vce0_vce_dec
// base address: 0x22000
#define mmVCE_STATUS 0x0a01
#define mmVCE_STATUS_BASE_IDX 0
#define mmVCE_VCPU_CNTL 0x0a05
#define mmVCE_VCPU_CNTL_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET0 0x0a09
#define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE0 0x0a0a
#define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b
#define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE1 0x0a0c
#define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d
#define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE2 0x0a0e
#define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f
#define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE3 0x0a10
#define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET4 0x0a11
#define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE4 0x0a12
#define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET5 0x0a13
#define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE5 0x0a14
#define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET6 0x0a15
#define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE6 0x0a16
#define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET7 0x0a17
#define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE7 0x0a18
#define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0
#define mmVCE_VCPU_CACHE_OFFSET8 0x0a19
#define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0
#define mmVCE_VCPU_CACHE_SIZE8 0x0a1a
#define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0
#define mmVCE_SOFT_RESET 0x0a48
#define mmVCE_SOFT_RESET_BASE_IDX 0
#define mmVCE_RB_BASE_LO2 0x0a5b
#define mmVCE_RB_BASE_LO2_BASE_IDX 0
#define mmVCE_RB_BASE_HI2 0x0a5c
#define mmVCE_RB_BASE_HI2_BASE_IDX 0
#define mmVCE_RB_SIZE2 0x0a5d
#define mmVCE_RB_SIZE2_BASE_IDX 0
#define mmVCE_RB_RPTR2 0x0a5e
#define mmVCE_RB_RPTR2_BASE_IDX 0
#define mmVCE_RB_WPTR2 0x0a5f
#define mmVCE_RB_WPTR2_BASE_IDX 0
#define mmVCE_RB_BASE_LO 0x0a60
#define mmVCE_RB_BASE_LO_BASE_IDX 0
#define mmVCE_RB_BASE_HI 0x0a61
#define mmVCE_RB_BASE_HI_BASE_IDX 0
#define mmVCE_RB_SIZE 0x0a62
#define mmVCE_RB_SIZE_BASE_IDX 0
#define mmVCE_RB_RPTR 0x0a63
#define mmVCE_RB_RPTR_BASE_IDX 0
#define mmVCE_RB_WPTR 0x0a64
#define mmVCE_RB_WPTR_BASE_IDX 0
#define mmVCE_RB_ARB_CTRL 0x0a9f
#define mmVCE_RB_ARB_CTRL_BASE_IDX 0
#define mmVCE_CLOCK_GATING_A 0x0abe
#define mmVCE_CLOCK_GATING_A_BASE_IDX 0
#define mmVCE_CLOCK_GATING_B 0x0abf
#define mmVCE_CLOCK_GATING_B_BASE_IDX 0
#define mmVCE_RB_BASE_LO3 0x0ad4
#define mmVCE_RB_BASE_LO3_BASE_IDX 0
#define mmVCE_RB_BASE_HI3 0x0ad5
#define mmVCE_RB_BASE_HI3_BASE_IDX 0
#define mmVCE_RB_SIZE3 0x0ad6
#define mmVCE_RB_SIZE3_BASE_IDX 0
#define mmVCE_RB_RPTR3 0x0ad7
#define mmVCE_RB_RPTR3_BASE_IDX 0
#define mmVCE_RB_WPTR3 0x0ad8
#define mmVCE_RB_WPTR3_BASE_IDX 0
#define mmVCE_SYS_INT_EN 0x0b00
#define mmVCE_SYS_INT_EN_BASE_IDX 0
#define mmVCE_SYS_INT_ACK 0x0b01
#define mmVCE_SYS_INT_ACK_BASE_IDX 0
#define mmVCE_SYS_INT_STATUS 0x0b01Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.