drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h- Extension
.h- Size
- 46685 bytes
- Lines
- 489
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vce_4_0_SH_MASK_HEADER
#define _vce_4_0_SH_MASK_HEADER
// addressBlock: vce0_vce_dec
//VCE_STATUS
#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
#define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL
#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
#define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L
#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L
//VCE_VCPU_CNTL
#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
#define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1
#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15
#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
#define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L
#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L
//VCE_VCPU_CACHE_OFFSET0
#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE0
#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET1
#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE1
#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET2
#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE2
#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET3
#define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE3
#define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET4
#define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE4
#define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET5
#define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE5
#define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET6
#define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE6
#define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET7
#define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE7
#define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL
//VCE_VCPU_CACHE_OFFSET8
#define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0
#define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL
//VCE_VCPU_CACHE_SIZE8
#define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0
#define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL
//VCE_SOFT_RESET
#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
#define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1
#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2
#define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3
#define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4
#define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5
#define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6
#define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7
#define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8
#define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.