drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h- Extension
.h- Size
- 42274 bytes
- Lines
- 423
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_1_0_OFFSET_HEADER
#define _vcn_1_0_OFFSET_HEADER
// addressBlock: uvd_uvd_pg_dec
// base address: 0x1fb00
#define mmUVD_PGFSM_CONFIG 0x00c0
#define mmUVD_PGFSM_CONFIG_BASE_IDX 1
#define mmUVD_PGFSM_STATUS 0x00c1
#define mmUVD_PGFSM_STATUS_BASE_IDX 1
#define mmUVD_POWER_STATUS 0x00c4
#define mmUVD_POWER_STATUS_BASE_IDX 1
#define mmCC_UVD_HARVESTING 0x00c7
#define mmCC_UVD_HARVESTING_BASE_IDX 1
#define mmUVD_DPG_LMA_CTL 0x00d1
#define mmUVD_DPG_LMA_CTL_BASE_IDX 1
#define mmUVD_DPG_LMA_DATA 0x00d2
#define mmUVD_DPG_LMA_DATA_BASE_IDX 1
#define mmUVD_DPG_LMA_MASK 0x00d3
#define mmUVD_DPG_LMA_MASK_BASE_IDX 1
#define mmUVD_DPG_PAUSE 0x00d4
#define mmUVD_DPG_PAUSE_BASE_IDX 1
#define mmUVD_SCRATCH1 0x00d5
#define mmUVD_SCRATCH1_BASE_IDX 1
#define mmUVD_SCRATCH2 0x00d6
#define mmUVD_SCRATCH2_BASE_IDX 1
#define mmUVD_SCRATCH3 0x00d7
#define mmUVD_SCRATCH3_BASE_IDX 1
#define mmUVD_SCRATCH4 0x00d8
#define mmUVD_SCRATCH4_BASE_IDX 1
#define mmUVD_SCRATCH5 0x00d9
#define mmUVD_SCRATCH5_BASE_IDX 1
#define mmUVD_SCRATCH6 0x00da
#define mmUVD_SCRATCH6_BASE_IDX 1
#define mmUVD_SCRATCH7 0x00db
#define mmUVD_SCRATCH7_BASE_IDX 1
#define mmUVD_SCRATCH8 0x00dc
#define mmUVD_SCRATCH8_BASE_IDX 1
#define mmUVD_SCRATCH9 0x00dd
#define mmUVD_SCRATCH9_BASE_IDX 1
#define mmUVD_SCRATCH10 0x00de
#define mmUVD_SCRATCH10_BASE_IDX 1
#define mmUVD_SCRATCH11 0x00df
#define mmUVD_SCRATCH11_BASE_IDX 1
#define mmUVD_SCRATCH12 0x00e0
#define mmUVD_SCRATCH12_BASE_IDX 1
#define mmUVD_SCRATCH13 0x00e1
#define mmUVD_SCRATCH13_BASE_IDX 1
#define mmUVD_SCRATCH14 0x00e2
#define mmUVD_SCRATCH14_BASE_IDX 1
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7
#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
// addressBlock: uvd_uvdgendec
// base address: 0x1fc00
#define mmUVD_LCM_CGC_CNTRL 0x0123
#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185
#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192
#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193
#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5
#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1
// addressBlock: uvd_uvdnpdec
// base address: 0x20000
#define mmUVD_JPEG_CNTL 0x0200
#define mmUVD_JPEG_CNTL_BASE_IDX 1
#define mmUVD_JPEG_RB_BASE 0x0201
#define mmUVD_JPEG_RB_BASE_BASE_IDX 1
#define mmUVD_JPEG_RB_WPTR 0x0202
#define mmUVD_JPEG_RB_WPTR_BASE_IDX 1
#define mmUVD_JPEG_RB_RPTR 0x0203
#define mmUVD_JPEG_RB_RPTR_BASE_IDX 1
#define mmUVD_JPEG_RB_SIZE 0x0204
#define mmUVD_JPEG_RB_SIZE_BASE_IDX 1
#define mmUVD_JPEG_ADDR_CONFIG 0x021fAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.