drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h- Extension
.h- Size
- 99586 bytes
- Lines
- 1006
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_2_5_OFFSET_HEADER
#define _vcn_2_5_OFFSET_HEADER
// addressBlock: uvd0_mmsch_dec
// base address: 0x1e000
#define mmMMSCH_VF_VMID 0x000b
#define mmMMSCH_VF_VMID_BASE_IDX 0
#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
#define mmMMSCH_VF_CTX_SIZE 0x000e
#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_HOST 0x0012
#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_RESP 0x0013
#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
// addressBlock: uvd0_jpegnpdec
// base address: 0x1e200
#define mmUVD_JPEG_CNTL 0x0080
#define mmUVD_JPEG_CNTL_BASE_IDX 0
#define mmUVD_JPEG_RB_BASE 0x0081
#define mmUVD_JPEG_RB_BASE_BASE_IDX 0
#define mmUVD_JPEG_RB_WPTR 0x0082
#define mmUVD_JPEG_RB_WPTR_BASE_IDX 0
#define mmUVD_JPEG_RB_RPTR 0x0083
#define mmUVD_JPEG_RB_RPTR_BASE_IDX 0
#define mmUVD_JPEG_RB_SIZE 0x0084
#define mmUVD_JPEG_RB_SIZE_BASE_IDX 0
#define mmUVD_JPEG_DEC_SCRATCH0 0x0089
#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0
#define mmUVD_JPEG_INT_EN 0x008a
#define mmUVD_JPEG_INT_EN_BASE_IDX 0
#define mmUVD_JPEG_INT_STAT 0x008b
#define mmUVD_JPEG_INT_STAT_BASE_IDX 0
#define mmUVD_JPEG_PITCH 0x009f
#define mmUVD_JPEG_PITCH_BASE_IDX 0
#define mmUVD_JPEG_UV_PITCH 0x00a0
#define mmUVD_JPEG_UV_PITCH_BASE_IDX 0
#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1
#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0
#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2
#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0
#define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3
#define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0
#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4
#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5
#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
#define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6
#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0
#define mmJPEG_DEC_ADDR_MODE 0x00a7
#define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0
#define mmUVD_JPEG_GPCOM_CMD 0x00a9
#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0
#define mmUVD_JPEG_GPCOM_DATA0 0x00aa
#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0
#define mmUVD_JPEG_GPCOM_DATA1 0x00ab
#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0
#define mmUVD_JPEG_SCRATCH1 0x00ae
#define mmUVD_JPEG_SCRATCH1_BASE_IDX 0
#define mmUVD_JPEG_DEC_SOFT_RST 0x00af
#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0
// addressBlock: uvd0_uvd_jpeg_enc_dec
// base address: 0x1e300
#define mmUVD_JPEG_ENC_INT_EN 0x00c1
#define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0
#define mmUVD_JPEG_ENC_INT_STATUS 0x00c2
#define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0
#define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5
#define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0
#define mmUVD_JPEG_ENC_SCRATCH1 0x00ce
#define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0
// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
// base address: 0x1e380
#define mmUVD_JPEG_ENC_STATUS 0x00e5
#define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0
#define mmUVD_JPEG_ENC_PITCH 0x00e6
#define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0
#define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7
#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0
#define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8
#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0
#define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.