drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h- Extension
.h- Size
- 151232 bytes
- Lines
- 1463
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_2_6_0_OFFSET_HEADER
#define _vcn_2_6_0_OFFSET_HEADER
// addressBlock: uvd0_ecpudec
// base address: 0x1fd00
#define regUVD_VCPU_CACHE_OFFSET0 0x0140
#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE0 0x0141
#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET1 0x0142
#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE1 0x0143
#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET2 0x0144
#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE2 0x0145
#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET3 0x0146
#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE3 0x0147
#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET4 0x0148
#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE4 0x0149
#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET5 0x014a
#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE5 0x014b
#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET6 0x014c
#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE6 0x014d
#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET7 0x014e
#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE7 0x014f
#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1
#define regUVD_VCPU_CACHE_OFFSET8 0x0150
#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1
#define regUVD_VCPU_CACHE_SIZE8 0x0151
#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1
#define regUVD_VCPU_NONCACHE_OFFSET0 0x0152
#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1
#define regUVD_VCPU_NONCACHE_SIZE0 0x0153
#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1
#define regUVD_VCPU_NONCACHE_OFFSET1 0x0154
#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1
#define regUVD_VCPU_NONCACHE_SIZE1 0x0155
#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1
#define regUVD_VCPU_CNTL 0x0156
#define regUVD_VCPU_CNTL_BASE_IDX 1
#define regUVD_VCPU_PRID 0x0157
#define regUVD_VCPU_PRID_BASE_IDX 1
#define regUVD_VCPU_TRCE 0x0158
#define regUVD_VCPU_TRCE_BASE_IDX 1
#define regUVD_VCPU_TRCE_RD 0x0159
#define regUVD_VCPU_TRCE_RD_BASE_IDX 1
#define regUVD_VCPU_IND_INDEX 0x015b
#define regUVD_VCPU_IND_INDEX_BASE_IDX 1
#define regUVD_VCPU_IND_DATA 0x015c
#define regUVD_VCPU_IND_DATA_BASE_IDX 1
// addressBlock: uvd0_jpegnpdec
// base address: 0x1e200
#define regUVD_JPEG_CNTL 0x0080
#define regUVD_JPEG_CNTL_BASE_IDX 0
#define regUVD_JPEG_RB_BASE 0x0081
#define regUVD_JPEG_RB_BASE_BASE_IDX 0
#define regUVD_JPEG_RB_WPTR 0x0082
#define regUVD_JPEG_RB_WPTR_BASE_IDX 0
#define regUVD_JPEG_RB_RPTR 0x0083
#define regUVD_JPEG_RB_RPTR_BASE_IDX 0
#define regUVD_JPEG_RB_SIZE 0x0084
#define regUVD_JPEG_RB_SIZE_BASE_IDX 0
#define regUVD_JPEG_DEC_CNT 0x0085
#define regUVD_JPEG_DEC_CNT_BASE_IDX 0
#define regUVD_JPEG_SPS_INFO 0x0086
#define regUVD_JPEG_SPS_INFO_BASE_IDX 0
#define regUVD_JPEG_SPS1_INFO 0x0087
#define regUVD_JPEG_SPS1_INFO_BASE_IDX 0
#define regUVD_JPEG_RE_TIMER 0x0088
#define regUVD_JPEG_RE_TIMER_BASE_IDX 0
#define regUVD_JPEG_DEC_SCRATCH0 0x0089
#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0
#define regUVD_JPEG_INT_EN 0x008a
#define regUVD_JPEG_INT_EN_BASE_IDX 0
#define regUVD_JPEG_INT_STAT 0x008bAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.