drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_offset.h- Extension
.h- Size
- 158827 bytes
- Lines
- 1543
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_3_0_0_OFFSET_HEADER
#define _vcn_3_0_0_OFFSET_HEADER
// addressBlock: uvd0_mmsch_dec
// base address: 0x1e000
#define mmMMSCH_UCODE_ADDR 0x0000
#define mmMMSCH_UCODE_ADDR_BASE_IDX 0
#define mmMMSCH_UCODE_DATA 0x0001
#define mmMMSCH_UCODE_DATA_BASE_IDX 0
#define mmMMSCH_SRAM_ADDR 0x0002
#define mmMMSCH_SRAM_ADDR_BASE_IDX 0
#define mmMMSCH_SRAM_DATA 0x0003
#define mmMMSCH_SRAM_DATA_BASE_IDX 0
#define mmMMSCH_VF_SRAM_OFFSET 0x0004
#define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX 0
#define mmMMSCH_DB_SRAM_OFFSET 0x0005
#define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX 0
#define mmMMSCH_CTX_SRAM_OFFSET 0x0006
#define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0
#define mmMMSCH_CTL 0x0007
#define mmMMSCH_CTL_BASE_IDX 0
#define mmMMSCH_INTR 0x0008
#define mmMMSCH_INTR_BASE_IDX 0
#define mmMMSCH_INTR_ACK 0x0009
#define mmMMSCH_INTR_ACK_BASE_IDX 0
#define mmMMSCH_INTR_STATUS 0x000a
#define mmMMSCH_INTR_STATUS_BASE_IDX 0
#define mmMMSCH_VF_VMID 0x000b
#define mmMMSCH_VF_VMID_BASE_IDX 0
#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
#define mmMMSCH_VF_CTX_SIZE 0x000e
#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
#define mmMMSCH_VF_GPCOM_ADDR_LO 0x000f
#define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
#define mmMMSCH_VF_GPCOM_ADDR_HI 0x0010
#define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
#define mmMMSCH_VF_GPCOM_SIZE 0x0011
#define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_HOST 0x0012
#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_RESP 0x0013
#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_0 0x0014
#define mmMMSCH_VF_MAILBOX_0_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_0_RESP 0x0015
#define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_1 0x0016
#define mmMMSCH_VF_MAILBOX_1_BASE_IDX 0
#define mmMMSCH_VF_MAILBOX_1_RESP 0x0017
#define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0
#define mmMMSCH_CNTL 0x001c
#define mmMMSCH_CNTL_BASE_IDX 0
#define mmMMSCH_NONCACHE_OFFSET0 0x001d
#define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX 0
#define mmMMSCH_NONCACHE_SIZE0 0x001e
#define mmMMSCH_NONCACHE_SIZE0_BASE_IDX 0
#define mmMMSCH_NONCACHE_OFFSET1 0x001f
#define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX 0
#define mmMMSCH_NONCACHE_SIZE1 0x0020
#define mmMMSCH_NONCACHE_SIZE1_BASE_IDX 0
#define mmMMSCH_PROC_STATE1 0x0026
#define mmMMSCH_PROC_STATE1_BASE_IDX 0
#define mmMMSCH_LAST_MC_ADDR 0x0027
#define mmMMSCH_LAST_MC_ADDR_BASE_IDX 0
#define mmMMSCH_LAST_MEM_ACCESS_HI 0x0028
#define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0
#define mmMMSCH_LAST_MEM_ACCESS_LO 0x0029
#define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0
#define mmMMSCH_IOV_ACTIVE_FCN_ID 0x002a
#define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 0
#define mmMMSCH_SCRATCH_0 0x002b
#define mmMMSCH_SCRATCH_0_BASE_IDX 0
#define mmMMSCH_SCRATCH_1 0x002c
#define mmMMSCH_SCRATCH_1_BASE_IDX 0
#define mmMMSCH_GPUIOV_SCH_BLOCK_0 0x002d
#define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_CMD_CONTROL_0 0x002e
#define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_CMD_STATUS_0 0x002f
#define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030
#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031
#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032
#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0
#define mmMMSCH_GPUIOV_DW6_0 0x0033Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.