drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h- Extension
.h- Size
- 187442 bytes
- Lines
- 1798
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_4_0_5_OFFSET_HEADER
#define _vcn_4_0_5_OFFSET_HEADER
// addressBlock: uvd_uvddec
// base address: 0x1fb00
#define regUVD_CGC_GATE 0x00c1
#define regUVD_CGC_GATE_BASE_IDX 1
#define regUVD_CGC_CTRL 0x00c2
#define regUVD_CGC_CTRL_BASE_IDX 1
#define regAVM_SUVD_CGC_GATE 0x00c4
#define regAVM_SUVD_CGC_GATE_BASE_IDX 1
#define regCDEFE_SUVD_CGC_GATE 0x00c4
#define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1
#define regEFC_SUVD_CGC_GATE 0x00c4
#define regEFC_SUVD_CGC_GATE_BASE_IDX 1
#define regENT_SUVD_CGC_GATE 0x00c4
#define regENT_SUVD_CGC_GATE_BASE_IDX 1
#define regIME_SUVD_CGC_GATE 0x00c4
#define regIME_SUVD_CGC_GATE_BASE_IDX 1
#define regPPU_SUVD_CGC_GATE 0x00c4
#define regPPU_SUVD_CGC_GATE_BASE_IDX 1
#define regSAOE_SUVD_CGC_GATE 0x00c4
#define regSAOE_SUVD_CGC_GATE_BASE_IDX 1
#define regSCM_SUVD_CGC_GATE 0x00c4
#define regSCM_SUVD_CGC_GATE_BASE_IDX 1
#define regSDB_SUVD_CGC_GATE 0x00c4
#define regSDB_SUVD_CGC_GATE_BASE_IDX 1
#define regSIT0_NXT_SUVD_CGC_GATE 0x00c4
#define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1
#define regSIT1_NXT_SUVD_CGC_GATE 0x00c4
#define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1
#define regSIT2_NXT_SUVD_CGC_GATE 0x00c4
#define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1
#define regSIT_SUVD_CGC_GATE 0x00c4
#define regSIT_SUVD_CGC_GATE_BASE_IDX 1
#define regSMPA_SUVD_CGC_GATE 0x00c4
#define regSMPA_SUVD_CGC_GATE_BASE_IDX 1
#define regSMP_SUVD_CGC_GATE 0x00c4
#define regSMP_SUVD_CGC_GATE_BASE_IDX 1
#define regSRE_SUVD_CGC_GATE 0x00c4
#define regSRE_SUVD_CGC_GATE_BASE_IDX 1
#define regUVD_MPBE0_SUVD_CGC_GATE 0x00c4
#define regUVD_MPBE0_SUVD_CGC_GATE_BASE_IDX 1
#define regUVD_MPBE1_SUVD_CGC_GATE 0x00c4
#define regUVD_MPBE1_SUVD_CGC_GATE_BASE_IDX 1
#define regUVD_SUVD_CGC_GATE 0x00c4
#define regUVD_SUVD_CGC_GATE_BASE_IDX 1
#define regAVM_SUVD_CGC_GATE2 0x00c5
#define regAVM_SUVD_CGC_GATE2_BASE_IDX 1
#define regCDEFE_SUVD_CGC_GATE2 0x00c5
#define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1
#define regDBR_SUVD_CGC_GATE2 0x00c5
#define regDBR_SUVD_CGC_GATE2_BASE_IDX 1
#define regENT_SUVD_CGC_GATE2 0x00c5
#define regENT_SUVD_CGC_GATE2_BASE_IDX 1
#define regIME_SUVD_CGC_GATE2 0x00c5
#define regIME_SUVD_CGC_GATE2_BASE_IDX 1
#define regMPC1_SUVD_CGC_GATE2 0x00c5
#define regMPC1_SUVD_CGC_GATE2_BASE_IDX 1
#define regSAOE_SUVD_CGC_GATE2 0x00c5
#define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1
#define regSDB_SUVD_CGC_GATE2 0x00c5
#define regSDB_SUVD_CGC_GATE2_BASE_IDX 1
#define regSIT0_NXT_SUVD_CGC_GATE2 0x00c5
#define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1
#define regSIT1_NXT_SUVD_CGC_GATE2 0x00c5
#define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1
#define regSIT2_NXT_SUVD_CGC_GATE2 0x00c5
#define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1
#define regSIT_SUVD_CGC_GATE2 0x00c5
#define regSIT_SUVD_CGC_GATE2_BASE_IDX 1
#define regSMPA_SUVD_CGC_GATE2 0x00c5
#define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1
#define regSMP_SUVD_CGC_GATE2 0x00c5
#define regSMP_SUVD_CGC_GATE2_BASE_IDX 1
#define regSRE_SUVD_CGC_GATE2 0x00c5
#define regSRE_SUVD_CGC_GATE2_BASE_IDX 1
#define regUVD_MPBE0_SUVD_CGC_GATE2 0x00c5
#define regUVD_MPBE0_SUVD_CGC_GATE2_BASE_IDX 1
#define regUVD_MPBE1_SUVD_CGC_GATE2 0x00c5
#define regUVD_MPBE1_SUVD_CGC_GATE2_BASE_IDX 1
#define regUVD_SUVD_CGC_GATE2 0x00c5
#define regUVD_SUVD_CGC_GATE2_BASE_IDX 1
#define regAVM_SUVD_CGC_CTRL 0x00c6
#define regAVM_SUVD_CGC_CTRL_BASE_IDX 1
#define regCDEFE_SUVD_CGC_CTRL 0x00c6
#define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1
#define regDBR_SUVD_CGC_CTRL 0x00c6Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.