drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h- Extension
.h- Size
- 184290 bytes
- Lines
- 1784
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_5_3_0_OFFSET_HEADER
#define _vcn_5_3_0_OFFSET_HEADER
// addressBlock: uvdctxind
// base address: 0x0
#define ixUVD_CGC_MEM_CTRL 0x0000
#define ixUVD_CGC_CTRL2 0x0001
#define ixUVD_CGC_MEM_DS_CTRL 0x0002
#define ixUVD_CGC_MEM_SD_CTRL 0x0003
#define ixUVD_SW_SCRATCH_00 0x0004
#define ixUVD_SW_SCRATCH_01 0x0005
#define ixUVD_SW_SCRATCH_02 0x0006
#define ixUVD_SW_SCRATCH_03 0x0007
#define ixUVD_SW_SCRATCH_04 0x0008
#define ixUVD_SW_SCRATCH_05 0x0009
#define ixUVD_SW_SCRATCH_06 0x000a
#define ixUVD_SW_SCRATCH_07 0x000b
#define ixUVD_SW_SCRATCH_08 0x000c
#define ixUVD_SW_SCRATCH_09 0x000d
#define ixUVD_SW_SCRATCH_10 0x000e
#define ixUVD_SW_SCRATCH_11 0x000f
#define ixUVD_SW_SCRATCH_12 0x0010
#define ixUVD_SW_SCRATCH_13 0x0011
#define ixUVD_SW_SCRATCH_14 0x0012
#define ixUVD_SW_SCRATCH_15 0x0013
#define ixUVD_IH_SEM_CTRL 0x001e
// addressBlock: lmi_adp_indirect
// base address: 0x0
#define ixUVD_LMI_CRC0 0x0000
#define ixUVD_LMI_CRC1 0x0001
#define ixUVD_LMI_CRC2 0x0002
#define ixUVD_LMI_CRC3 0x0003
#define ixUVD_LMI_CRC10 0x000a
#define ixUVD_LMI_CRC11 0x000b
#define ixUVD_LMI_CRC12 0x000c
#define ixUVD_LMI_CRC13 0x000d
#define ixUVD_LMI_CRC14 0x000e
#define ixUVD_LMI_CRC15 0x000f
#define ixUVD_LMI_SWAP_CNTL2 0x0029
#define ixUVD_MEMCHECK_SYS_INT_EN 0x0134
#define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135
#define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136
#define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137
#define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138
#define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139
#define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140
#define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141
#define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142
#define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143
// addressBlock: uvd_uvd_pg_dec
// base address: 0x1f800
#define regUVD_IPX_DLDO_CONFIG 0x0000
#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
#define regUVD_IPX_DLDO_STATUS 0x0001
#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
#define regUVD_POWER_STATUS 0x0002
#define regUVD_POWER_STATUS_BASE_IDX 1
#define regUVD_JPEG_POWER_STATUS 0x0003
#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1
#define regUVD_MC_DJPEG_RD_SPACE 0x0007
#define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1
#define regUVD_MC_DJPEG_WR_SPACE 0x0008
#define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1
#define regUVD_PG_IND_INDEX 0x000c
#define regUVD_PG_IND_INDEX_BASE_IDX 1
#define regUVD_PG_IND_DATA 0x000e
#define regUVD_PG_IND_DATA_BASE_IDX 1
#define regCC_UVD_HARVESTING 0x000f
#define regCC_UVD_HARVESTING_BASE_IDX 1
#define regUVD_DPG_LMA_CTL 0x0011
#define regUVD_DPG_LMA_CTL_BASE_IDX 1
#define regUVD_DPG_LMA_DATA 0x0012
#define regUVD_DPG_LMA_DATA_BASE_IDX 1
#define regUVD_DPG_LMA_MASK 0x0013
#define regUVD_DPG_LMA_MASK_BASE_IDX 1
#define regUVD_DPG_PAUSE 0x0014
#define regUVD_DPG_PAUSE_BASE_IDX 1
#define regUVD_SCRATCH1 0x0015
#define regUVD_SCRATCH1_BASE_IDX 1
#define regUVD_SCRATCH2 0x0016
#define regUVD_SCRATCH2_BASE_IDX 1
#define regUVD_SCRATCH3 0x0017
#define regUVD_SCRATCH3_BASE_IDX 1
#define regUVD_SCRATCH4 0x0018
#define regUVD_SCRATCH4_BASE_IDX 1Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.