drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h- Extension
.h- Size
- 887590 bytes
- Lines
- 8263
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vcn_5_3_0_SH_MASK_HEADER
#define _vcn_5_3_0_SH_MASK_HEADER
// addressBlock: uvdctxind
//UVD_CGC_MEM_CTRL
#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe
#define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf
#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L
#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L
#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L
#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L
#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L
#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L
#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L
#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L
#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L
#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L
#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L
#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L
#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L
#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L
#define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L
#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L
#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L
//UVD_CGC_CTRL2
#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL
//UVD_CGC_MEM_DS_CTRL
#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0
#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1
#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2
#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3
#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4
#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5
#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6
#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7
#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8
#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9
#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa
#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc
#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd
#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe
#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf
#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L
#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L
#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L
#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L
#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L
#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L
#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L
#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L
#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L
#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L
#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L
#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L
#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L
#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L
#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L
//UVD_CGC_MEM_SD_CTRL
#define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0
#define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1
#define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2
#define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3
#define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4
#define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5
#define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6
#define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7
#define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8
#define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9
#define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xaAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.