drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h- Extension
.h- Size
- 110856 bytes
- Lines
- 1042
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vpe_2_0_0_OFFSET_HEADER
#define _vpe_2_0_0_OFFSET_HEADER
// addressBlock: vpe_vpec_vpecdec
// base address: 0x46000
#define regVPEC_DEC_START 0x0000
#define regVPEC_DEC_START_BASE_IDX 0
#define regVPEC_UCODE_ADDR 0x0001
#define regVPEC_UCODE_ADDR_BASE_IDX 0
#define regVPEC_UCODE_DATA 0x0002
#define regVPEC_UCODE_DATA_BASE_IDX 0
#define regVPEC_F32_CNTL 0x0003
#define regVPEC_F32_CNTL_BASE_IDX 0
#define regVPEC_MMHUB_CNTL 0x0004
#define regVPEC_MMHUB_CNTL_BASE_IDX 0
#define regVPEC_MMHUB_TRUSTLVL 0x0005
#define regVPEC_MMHUB_TRUSTLVL_BASE_IDX 0
#define regVPEC_VPEP_CTRL 0x0010
#define regVPEC_VPEP_CTRL_BASE_IDX 0
#define regVPEC_CLK_CTRL 0x0011
#define regVPEC_CLK_CTRL_BASE_IDX 0
#define regVPEC_COLLABORATE_CNTL 0x0012
#define regVPEC_COLLABORATE_CNTL_BASE_IDX 0
#define regVPEC_COLLABORATE_CFG 0x0013
#define regVPEC_COLLABORATE_CFG_BASE_IDX 0
#define regVPEC_POWER_CNTL 0x0014
#define regVPEC_POWER_CNTL_BASE_IDX 0
#define regVPEC_ZPR_CNTL 0x0015
#define regVPEC_ZPR_CNTL_BASE_IDX 0
#define regVPEC_CNTL 0x0016
#define regVPEC_CNTL_BASE_IDX 0
#define regVPEC_CNTL_DCC 0x0017
#define regVPEC_CNTL_DCC_BASE_IDX 0
#define regVPEC_CE_OP_MULTI_64B_BURST 0x0018
#define regVPEC_CE_OP_MULTI_64B_BURST_BASE_IDX 0
#define regVPEC_CNTL1 0x0019
#define regVPEC_CNTL1_BASE_IDX 0
#define regVPEC_CNTL2 0x001a
#define regVPEC_CNTL2_BASE_IDX 0
#define regVPEC_GB_ADDR_CONFIG 0x001b
#define regVPEC_GB_ADDR_CONFIG_BASE_IDX 0
#define regVPEC_GB_ADDR_CONFIG_READ 0x001c
#define regVPEC_GB_ADDR_CONFIG_READ_BASE_IDX 0
#define regVPEC_GB_ADDR_CONFIG_META 0x001d
#define regVPEC_GB_ADDR_CONFIG_META_BASE_IDX 0
#define regVPEC_PROCESS_QUANTUM0 0x001e
#define regVPEC_PROCESS_QUANTUM0_BASE_IDX 0
#define regVPEC_PROCESS_QUANTUM1 0x001f
#define regVPEC_PROCESS_QUANTUM1_BASE_IDX 0
#define regVPEC_CONTEXT_SWITCH_THRESHOLD 0x0020
#define regVPEC_CONTEXT_SWITCH_THRESHOLD_BASE_IDX 0
#define regVPEC_GLOBAL_QUANTUM 0x0021
#define regVPEC_GLOBAL_QUANTUM_BASE_IDX 0
#define regVPEC_WATCHDOG_CNTL 0x0025
#define regVPEC_WATCHDOG_CNTL_BASE_IDX 0
#define regVPEC_ATOMIC_CNTL 0x0026
#define regVPEC_ATOMIC_CNTL_BASE_IDX 0
#define regVPEC_UCODE_VERSION 0x0027
#define regVPEC_UCODE_VERSION_BASE_IDX 0
#define regVPEC_MEMREQ_BURST_CNTL 0x0028
#define regVPEC_MEMREQ_BURST_CNTL_BASE_IDX 0
#define regVPEC_TIMESTAMP_CNTL 0x0029
#define regVPEC_TIMESTAMP_CNTL_BASE_IDX 0
#define regVPEC_GLOBAL_TIMESTAMP_LO 0x002a
#define regVPEC_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
#define regVPEC_GLOBAL_TIMESTAMP_HI 0x002b
#define regVPEC_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
#define regVPEC_FREEZE 0x002c
#define regVPEC_FREEZE_BASE_IDX 0
#define regVPEC_CE_CTRL 0x002d
#define regVPEC_CE_CTRL_BASE_IDX 0
#define regVPEC_RELAX_ORDERING_LUT 0x002e
#define regVPEC_RELAX_ORDERING_LUT_BASE_IDX 0
#define regVPEC_CREDIT_CNTL 0x002f
#define regVPEC_CREDIT_CNTL_BASE_IDX 0
#define regVPEC_SCRATCH_RAM_DATA 0x0030
#define regVPEC_SCRATCH_RAM_DATA_BASE_IDX 0
#define regVPEC_SCRATCH_RAM_ADDR 0x0031
#define regVPEC_SCRATCH_RAM_ADDR_BASE_IDX 0
#define regVPEC_QUEUE_RESET_REQ 0x0032
#define regVPEC_QUEUE_RESET_REQ_BASE_IDX 0
#define regVPEC_MAILBOX0 0x0040
#define regVPEC_MAILBOX0_BASE_IDX 0
#define regVPEC_MAILBOX1 0x0041
#define regVPEC_MAILBOX1_BASE_IDX 0
#define regVPEC_MAILBOX2 0x0042
#define regVPEC_MAILBOX2_BASE_IDX 0
#define regVPEC_MAILBOX3 0x0043Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.