drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h- Extension
.h- Size
- 323859 bytes
- Lines
- 3163
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vpe_2_0_0_SH_MASK_HEADER
#define _vpe_2_0_0_SH_MASK_HEADER
// addressBlock: vpe_vpec_vpecdec
//VPEC_DEC_START
#define VPEC_DEC_START__START__SHIFT 0x0
#define VPEC_DEC_START__START_MASK 0xFFFFFFFFL
//VPEC_UCODE_ADDR
#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0
#define VPEC_UCODE_ADDR__THID__SHIFT 0xf
#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL
#define VPEC_UCODE_ADDR__THID_MASK 0x00008000L
//VPEC_UCODE_DATA
#define VPEC_UCODE_DATA__VALUE__SHIFT 0x0
#define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
//VPEC_F32_CNTL
#define VPEC_F32_CNTL__HALT__SHIFT 0x0
#define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8
#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9
#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa
#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc
#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd
#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe
#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10
#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18
#define VPEC_F32_CNTL__HALT_MASK 0x00000001L
#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL
#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L
#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L
#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L
#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L
#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L
#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L
#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L
#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L
//VPEC_MMHUB_CNTL
#define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
#define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
//VPEC_MMHUB_TRUSTLVL
#define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x0
#define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x4
#define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x8
#define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0xc
#define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x10
#define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x14
#define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x18
#define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x1c
#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000FL
#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000F0L
#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000F00L
#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000F000L
#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000F0000L
#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00F00000L
#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0F000000L
#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xF0000000L
//VPEC_VPEP_CTRL
#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0
#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1
#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0__SHIFT 0x16
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1__SHIFT 0x17
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2__SHIFT 0x18
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0__SHIFT 0x19
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1__SHIFT 0x1a
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2__SHIFT 0x1b
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT__SHIFT 0x1c
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN__SHIFT 0x1d
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f
#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L
#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L
#define VPEC_VPEP_CTRL__RESERVED_MASK 0x003FFFFCL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0_MASK 0x00400000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1_MASK 0x00800000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2_MASK 0x01000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0_MASK 0x02000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1_MASK 0x04000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2_MASK 0x08000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT_MASK 0x10000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN_MASK 0x20000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L
//VPEC_CLK_CTRL
#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x8
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x9
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK__SHIFT 0xa
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK__SHIFT 0xbAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.