drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_6_1_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_6_1_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_6_1_0_sh_mask.h- Extension
.h- Size
- 444963 bytes
- Lines
- 4394
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _vpe_6_1_0_SH_MASK_HEADER
#define _vpe_6_1_0_SH_MASK_HEADER
// addressBlock: vpe_vpedec
//VPEC_DEC_START
#define VPEC_DEC_START__START__SHIFT 0x0
#define VPEC_DEC_START__START_MASK 0xFFFFFFFFL
//VPEC_UCODE_ADDR
#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0
#define VPEC_UCODE_ADDR__THID__SHIFT 0xf
#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL
#define VPEC_UCODE_ADDR__THID_MASK 0x00008000L
//VPEC_UCODE_DATA
#define VPEC_UCODE_DATA__VALUE__SHIFT 0x0
#define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
//VPEC_F32_CNTL
#define VPEC_F32_CNTL__HALT__SHIFT 0x0
#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8
#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9
#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa
#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc
#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd
#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe
#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10
#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18
#define VPEC_F32_CNTL__HALT_MASK 0x00000001L
#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L
#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L
#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L
#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L
#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L
#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L
#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L
#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L
//VPEC_VPEP_CTRL
#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0
#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1
#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f
#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L
#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L
#define VPEC_VPEP_CTRL__RESERVED_MASK 0x3FFFFFFCL
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L
#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L
//VPEC_CLK_CTRL
#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1
#define VPEC_CLK_CTRL__RESERVED__SHIFT 0x2
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x18
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x19
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x1a
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f
#define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L
#define VPEC_CLK_CTRL__RESERVED_MASK 0x00FFFFFCL
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x01000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x02000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x04000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L
#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L
//VPEC_PG_CNTL
#define VPEC_PG_CNTL__PG_EN__SHIFT 0x0
#define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1
#define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L
#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL
//VPEC_POWER_CNTL
#define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x8
#define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000100L
//VPEC_CNTL
#define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0
#define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2
#define VPEC_CNTL__DATA_SWAP__SHIFT 0x3
#define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5
#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6
#define VPEC_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8
#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9
#define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa
#define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb
#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe
#define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf
#define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10
#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
#define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.