drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h
Extension
.h
Size
6153 bytes
Lines
137
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __IRQSRCS_GFX_12_1_0_H__
#define __IRQSRCS_GFX_12_1_0_H__

/* 0x0 UTCL2 has encountered a fault scenario */
#define GFX_12_1_0__SRCID__UTCL2_FAULT				0
/* 0x1 UTCL2 has encountered a retry scenario */
#define GFX_12_1_0__SRCID__UTCL2_RETRY				1
/* 0x2 UTCL2 for data poisoning */
#define GFX_12_1_0__SRCID__UTCL2_DATA_POISONING			2
/* 0x30 SDMA atomic*_rtn ops complete */
#define GFX_12_1_0__SRCID__SDMA_ATOMIC_RTN_DONE			48
/* 0x31 Trap */
#define GFX_12_1_0__SRCID__SDMA_TRAP				49
/* 0x32 SRBM write Protection */
#define GFX_12_1_0__SRCID__SDMA_SRBMWRITE			50
/* 0x33 Context Empty */
#define GFX_12_1_0__SRCID__SDMA_CTXEMPTY			51
/* 0x34 SDMA New Run List */
#define GFX_12_1_0__SRCID__SDMA_PREEMPT				52
/* 0x35 sdma mid - command buffer preempt interrupt */
#define GFX_12_1_0__SRCID__SDMA_IB_PREEMPT			53
/* 0x36 Doorbell BE invalid */
#define GFX_12_1_0__SRCID__SDMA_DOORBELL_INVALID		54
/* 0x37 Queue hang or Command timeout */
#define GFX_12_1_0__SRCID__SDMA_QUEUE_HANG			55
/* 0x38 SDMA atomic CMPSWAP loop timeout */
#define GFX_12_1_0__SRCID__SDMA_ATOMIC_TIMEOUT			56
/* 0x39 SRBM read poll timeout */
#define GFX_12_1_0__SRCID__SDMA_POLL_TIMEOUT			57
/* 0x3A Page retry  timeout after UTCL2 return nack = 1 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_TIMEOUT			58
/* 0x3B Page Null from UTCL2 when nack = 2 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_NULL			59
/* 0x3C Page Fault Error from UTCL2 when nack = 3 */
#define GFX_12_1_0__SRCID__SDMA_PAGE_FAULT			60
/* 0x3D MC or SEM address in VM hole */
#define GFX_12_1_0__SRCID__SDMA_INVALID_ADDR 			61
/* 0x3E ECC Error */
#define GFX_12_1_0__SRCID__SDMA_ECC				62
/* 0x3F SDMA Frozen */
#define GFX_12_1_0__SRCID__SDMA_FROZEN				63
/* 0x40 SRAM ECC Error */
#define GFX_12_1_0__SRCID__SDMA_SRAM_ECC			64
/* 0x41 GPF(Sem incomplete timeout) */
#define GFX_12_1_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT		65
/* 0x42 Semaphore wait fail timeout */
#define GFX_12_1_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT		66
/* 0x43 Wptr less than Rptr in active queue */
#define GFX_12_1_0__SRCID__SDMA_INVALID_RB_PTR 			67
/* 0x44 BE command exception */
#define GFX_12_1_0__SRCID__SDMA_BE_EXCEPTION 			68
/* 0x46 User fence. inherit from gfx v12_0 for gfx user queue */
#define GFX_12_1_0__SRCID__SDMA_FENCE				70
/* 0xB0 CP_INTERRUPT pkt in RB */
#define GFX_12_1_0__SRCID__CP_RB_INT_PKT 			176
/* 0xB1 CP_INTERRUPT pkt in IB1 */
#define GFX_12_1_0__SRCID__CP_IB1_INT_PKT			177
/* 0xB2 CP_INTERRUPT pkt in IB2 */
#define GFX_12_1_0__SRCID__CP_IB2_INT_PKT			178
/* 0xB3 DMA Watch Interrupt */
#define GFX_12_1_0__SRCID__CP_DMA_WATCH_INTERRUPT 		179
/* 0xB4 PM4 Pkt Rsvd Bits Error */
#define GFX_12_1_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR		180
/* 0xB5 End-of-Pipe Interrupt */
#define GFX_12_1_0__SRCID__CP_EOP_INTERRUPT			181
/* 0xB7 Bad Opcode Error */
#define GFX_12_1_0__SRCID__CP_BAD_OPCODE_ERROR			183
/* 0xB8 Privileged Register Fault */
#define GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT			184
/* 0xB9 Privileged Instr Fault */
#define GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT			185
/* 0xBA Wait Memory Semaphore Fault (Sync Object Fault) */
#define GFX_12_1_0__SRCID__CP_WAIT_MEM_SEM_FAULT		186
/* 0xBB Context Empty Interrupt */
#define GFX_12_1_0__SRCID__CP_CTX_EMPTY_INTERRUPT		187
/* 0xBC Context Busy Interrupt */
#define GFX_12_1_0__SRCID__CP_CTX_BUSY_INTERRUPT		188
/* 0xC0 CP.ME Wait_Reg_Mem Poll Timeout */
#define GFX_12_1_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT	192
/* 0xC1 Surface Probe Fault Signal Incomplete */
#define GFX_12_1_0__SRCID__CP_SIG_INCOMPLETE			193
/* 0xC2 Preemption Ack-wledge */
#define GFX_12_1_0__SRCID__CP_PREEMPT_ACK			194
/* 0xC3 General Protection Fault (GPF) */
#define GFX_12_1_0__SRCID__CP_GPF				195
/* 0xC4 GDS Alloc Error */
#define GFX_12_1_0__SRCID__CP_GDS_ALLOC_ERROR			196
/* 0xC5 ECC Error */
#define GFX_12_1_0__SRCID__CP_ECC_ERROR				197
/* 0xC8 Unattached VM Doorbell Received */

Annotation

Implementation Notes