drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h
Extension: .h
Size: 4410 bytes
Lines: 63
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __IRQSRCS_ISP_4_1_H__
#define __IRQSRCS_ISP_4_1_H__


#define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT			0x12	// Semaphore wait fail timeout
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT		0x13	// Semaphore wait incomplete timeout
#define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT		0x14	// Semaphore signal incomplete timeout
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED			0x15	// Ringbuffer base5 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5			        0x16	// Ringbuffer write point 5 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED			0x17	// Ringbuffer base6 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6			        0x18	// Ringbuffer write point 6 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED			0x19	// Ringbuffer base7 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7			        0x1A	// Ringbuffer write point 7 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED			0x1B	// Ringbuffer base8 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8			        0x1C	// Ringbuffer write point 8 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED			0x00    // Ringbuffer base9 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9			        0x01    // Ringbuffer write point 9 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED			0x02    // Ringbuffer base10 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10			        0x03    // Ringbuffer write point 10 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED			0x04    // Ringbuffer base11 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11			        0x05    // Ringbuffer write point 11 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED			0x06    // Ringbuffer base12 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12			        0x07    // Ringbuffer write point 12 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED			0x08    // Ringbuffer base13 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13			        0x09    // Ringbuffer write point 13 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED			0x0A    // Ringbuffer base14 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14			        0x0B    // Ringbuffer write point 14 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED			0x0C    // Ringbuffer base15 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15			        0x0D    // Ringbuffer write point 15 changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED			0x0E    // Ringbuffer base16 address changed
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16			        0x0F    // Ringbuffer write point 16 changed
#define ISP_4_1__SRCID__ISP_MIPI0			                0x29	// MIPI0 interrupt
#define ISP_4_1__SRCID__ISP_MIPI1			                0x2A	// MIPI1 interrupt
#define ISP_4_1__SRCID__ISP_I2C0			                0x2B	// I2C0 PAD interrupt
#define ISP_4_1__SRCID__ISP_I2C1			                0x2C	// I2C1 PAD interrupt
#define ISP_4_1__SRCID__ISP_FLASH0			                0x2D	// Flash0 interrupt
#define ISP_4_1__SRCID__ISP_FLASH1			                0x2E	// Flash1 interrupt
#define ISP_4_1__SRCID__ISP_DEBUG			                0x2F	// Debug information

#endif

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.