drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

Extension

.h

Size

14776 bytes

Lines

300

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _IVSRCID_VISLANDS30_H_
#define _IVSRCID_VISLANDS30_H_


// IV Source IDs

#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT		            7	    // 0x07	
#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP		            8	    // 0x08	
#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT		            9	    // 0x09	
#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP  		            10	    // 0x0a	
#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT		            11	    // 0x0b	
#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP		            12	    // 0x0c	
#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT		            13	    // 0x0d  	
#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP		            14	    // 0x0e  	
#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT		            15	    // 0x0f	
#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP		            16	    // 0x10  	
#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT		            17	    // 0x11      	
#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT                  0

#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP		            18	    // 0x12  	
#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP                    0

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0           19      // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0           7

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1           19      // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1           8

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2           19      // 0x13
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2           9

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS          19      // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS          10

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC               19      // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC               11

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL             19      // 0x13
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL             12

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0           20      // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0           7

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1           20      // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1           8

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2           20      // 0x14
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2           9

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS          20      // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS          10

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC               20      // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC               11

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL             20      // 0x14
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL             12

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0           21      // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0           7

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1           21      // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1           8

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2           21      // 0x15
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2           9

#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS          21      // 0x15
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS          10

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.