drivers/gpu/drm/amd/include/vega10_enum.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/vega10_enum.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/include/vega10_enum.h
Extension: .h
Size: 838592 bytes
Lines: 22533
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#if !defined (_vega10_ENUM_HEADER)
#define _vega10_ENUM_HEADER

#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO                      BLEND_ZERO
#define GL__ONE                       BLEND_ONE
#define GL__SRC_COLOR                 BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR                 BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA                 BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif

/*******************************************************
 * GDS DATA_TYPE Enums
 *******************************************************/

#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
#define ENUMS_GDS_PERFCOUNT_SELECT_H
typedef enum GDS_PERFCOUNT_SELECT {
 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
 GDS_PERF_SEL_DS_BANK_CONFL = 1,
 GDS_PERF_SEL_WBUF_FLUSH = 2,
 GDS_PERF_SEL_WR_COMP = 3,
 GDS_PERF_SEL_WBUF_WR = 4,
 GDS_PERF_SEL_RBUF_HIT = 5,
 GDS_PERF_SEL_RBUF_MISS = 6,
 GDS_PERF_SEL_SE0_SH0_NORET = 7,
 GDS_PERF_SEL_SE0_SH0_RET = 8,
 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
 GDS_PERF_SEL_SE0_SH1_NORET = 21,
 GDS_PERF_SEL_SE0_SH1_RET = 22,
 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
 GDS_PERF_SEL_SE1_SH0_NORET = 35,
 GDS_PERF_SEL_SE1_SH0_RET = 36,
 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 GDS_PERF_SEL_SE1_SH1_RET = 50,
 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.