drivers/gpu/drm/amd/pm/amdgpu_dpm.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/amdgpu_dpm.c- Extension
.c- Size
- 52082 bytes
- Lines
- 2120
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hamdgpu_atombios.hamdgpu_i2c.hamdgpu_dpm.hatom.hamd_pcie.hamdgpu_display.hhwmgr.hlinux/power_supply.hamdgpu_smu.h
Detected Declarations
function filesfunction amdgpu_dpm_get_mclkfunction amdgpu_dpm_set_powergating_by_smufunction amdgpu_dpm_set_gfx_power_up_by_imufunction amdgpu_dpm_baco_enterfunction amdgpu_dpm_baco_exitfunction amdgpu_dpm_set_mp1_statefunction amdgpu_dpm_is_baco_supportedfunction amdgpu_dpm_mode2_resetfunction amdgpu_dpm_enable_gfx_featuresfunction amdgpu_dpm_baco_resetfunction amdgpu_dpm_is_mode1_reset_supportedfunction amdgpu_dpm_mode1_resetfunction amdgpu_dpm_is_link_reset_supportedfunction amdgpu_dpm_link_resetfunction amdgpu_dpm_switch_power_profilefunction amdgpu_dpm_pause_power_profilefunction amdgpu_dpm_set_xgmi_pstatefunction amdgpu_dpm_set_df_cstatefunction amdgpu_dpm_get_pm_policy_infofunction amdgpu_dpm_set_pm_policyfunction amdgpu_dpm_enable_mgpu_fan_boostfunction amdgpu_dpm_set_clockgating_by_smufunction amdgpu_dpm_smu_i2c_bus_accessfunction amdgpu_pm_acpi_event_handlerfunction amdgpu_dpm_read_sensorfunction amdgpu_dpm_get_apu_thermal_limitfunction amdgpu_dpm_set_apu_thermal_limitfunction amdgpu_dpm_compute_clocksfunction amdgpu_dpm_enable_uvdfunction amdgpu_dpm_enable_vcnfunction amdgpu_dpm_enable_vcefunction amdgpu_dpm_enable_jpegfunction amdgpu_dpm_enable_vpefunction amdgpu_pm_load_smu_firmwarefunction amdgpu_dpm_handle_passthrough_sbrfunction amdgpu_dpm_send_hbm_bad_pages_numfunction amdgpu_dpm_send_hbm_bad_channel_flagfunction amdgpu_dpm_send_rma_reasonfunction amdgpu_dpm_reset_sdma_is_supportedfunction amdgpu_dpm_reset_sdmafunction amdgpu_dpm_reset_vcnfunction amdgpu_dpm_reset_vcn_is_supportedfunction amdgpu_dpm_get_dpm_freq_rangefunction amdgpu_dpm_set_soft_freq_rangefunction amdgpu_dpm_write_watermarks_tablefunction amdgpu_dpm_wait_for_eventfunction amdgpu_dpm_set_residency_gfxoff
Annotated Snippet
if (enable) {
adev->pm.dpm.uvd_active = true;
adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
} else {
adev->pm.dpm.uvd_active = false;
}
mutex_unlock(&adev->pm.mutex);
amdgpu_dpm_compute_clocks(adev);
return;
}
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);
if (ret)
drm_err(adev_to_drm(adev), "DPM %s uvd failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
}
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
{
int ret = 0;
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);
if (ret)
drm_err(adev_to_drm(adev), "DPM %s vcn failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
}
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
if (adev->family == AMDGPU_FAMILY_SI) {
mutex_lock(&adev->pm.mutex);
if (enable) {
adev->pm.dpm.vce_active = true;
/* XXX select vce level based on ring/task */
adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
} else {
adev->pm.dpm.vce_active = false;
}
mutex_unlock(&adev->pm.mutex);
amdgpu_dpm_compute_clocks(adev);
return;
}
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);
if (ret)
drm_err(adev_to_drm(adev), "DPM %s vce failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
}
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);
if (ret)
drm_err(adev_to_drm(adev), "Dpm %s jpeg failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
}
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);
if (ret)
drm_err(adev_to_drm(adev), "DPM %s vpe failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
}
int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int r = 0;
if (!pp_funcs || !pp_funcs->load_firmware ||
(is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU)))
return 0;
mutex_lock(&adev->pm.mutex);
r = pp_funcs->load_firmware(adev->powerplay.pp_handle);
if (r) {
pr_err("smu firmware loading failed\n");
goto out;
}
if (smu_version)
Annotation
- Immediate include surface: `amdgpu.h`, `amdgpu_atombios.h`, `amdgpu_i2c.h`, `amdgpu_dpm.h`, `atom.h`, `amd_pcie.h`, `amdgpu_display.h`, `hwmgr.h`.
- Detected declarations: `function files`, `function amdgpu_dpm_get_mclk`, `function amdgpu_dpm_set_powergating_by_smu`, `function amdgpu_dpm_set_gfx_power_up_by_imu`, `function amdgpu_dpm_baco_enter`, `function amdgpu_dpm_baco_exit`, `function amdgpu_dpm_set_mp1_state`, `function amdgpu_dpm_is_baco_supported`, `function amdgpu_dpm_mode2_reset`, `function amdgpu_dpm_enable_gfx_features`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.