drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c- Extension
.c- Size
- 94749 bytes
- Lines
- 3361
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hamdgpu_pm.hcikd.hatom.hamdgpu_atombios.hamdgpu_dpm.hkv_dpm.hgfx_v7_0.hlinux/seq_file.hsmu/smu_7_0_0_d.hsmu/smu_7_0_0_sh_mask.hgca/gfx_7_2_d.hgca/gfx_7_2_sh_mask.hlegacy_dpm.h
Detected Declarations
function kv_convert_vid2_to_vid7function kv_convert_vid7_to_vid2function sumo_take_smu_controlfunction sumo_construct_sclk_voltage_mapping_tablefunction sumo_construct_vid_mapping_tablefunction kv_program_local_cac_tablefunction kv_program_pt_config_registersfunction kv_do_enable_didtfunction kv_enable_didtfunction kv_initialize_hardware_cac_managerfunction kv_enable_smc_cacfunction kv_process_firmware_headerfunction kv_enable_dpm_voltage_scalingfunction kv_set_dpm_intervalfunction kv_set_dpm_boot_statefunction kv_program_vcfunction kv_clear_vcfunction kv_set_divider_valuefunction kv_convert_8bit_index_to_voltagefunction kv_convert_2bit_index_to_voltagefunction kv_set_vidfunction kv_set_atfunction kv_dpm_power_level_enablefunction kv_start_dpmfunction kv_stop_dpmfunction kv_start_amfunction kv_reset_amfunction kv_freeze_sclk_dpmfunction kv_force_lowest_validfunction kv_unforce_levelsfunction kv_update_sclk_tfunction kv_program_bootup_statefunction kv_enable_auto_thermal_throttlingfunction kv_upload_dpm_settingsfunction kv_get_clock_differencefunction kv_get_clk_bypassfunction kv_populate_uvd_tablefunction kv_populate_vce_tablefunction kv_populate_samu_tablefunction kv_populate_acp_tablefunction kv_calculate_dfs_bypass_settingsfunction kv_enable_ulvfunction kv_reset_acp_boot_levelfunction kv_update_current_psfunction kv_update_requested_psfunction kv_dpm_enable_bapmfunction kv_is_internal_thermal_sensorfunction kv_dpm_enable
Annotated Snippet
if (table[i].ulSupportedSCLK > prev_sclk) {
sclk_voltage_mapping_table->entries[n].sclk_frequency =
table[i].ulSupportedSCLK;
sclk_voltage_mapping_table->entries[n].vid_2bit =
table[i].usVoltageIndex;
prev_sclk = table[i].ulSupportedSCLK;
n++;
}
}
sclk_voltage_mapping_table->num_max_dpm_entries = n;
}
static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
struct sumo_vid_mapping_table *vid_mapping_table,
ATOM_AVAILABLE_SCLK_LIST *table)
{
u32 i, j;
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
if (table[i].ulSupportedSCLK != 0) {
if (table[i].usVoltageIndex >= SUMO_MAX_NUMBER_VOLTAGES)
continue;
vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
table[i].usVoltageID;
vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
table[i].usVoltageIndex;
}
}
for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
if (vid_mapping_table->entries[i].vid_7bit == 0) {
for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
if (vid_mapping_table->entries[j].vid_7bit != 0) {
vid_mapping_table->entries[i] =
vid_mapping_table->entries[j];
vid_mapping_table->entries[j].vid_7bit = 0;
break;
}
}
if (j == SUMO_MAX_NUMBER_VOLTAGES)
break;
}
}
vid_mapping_table->num_entries = i;
}
#if 0
static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 1, 4, 1 },
{ 2, 5, 1 },
{ 3, 4, 2 },
{ 4, 1, 1 },
{ 5, 5, 2 },
{ 6, 6, 1 },
{ 7, 9, 2 },
{ 0xffffffff }
};
static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 0xffffffff }
};
static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 0xffffffff }
};
static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 0xffffffff }
};
static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 0xffffffff }
};
static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = {
{ 0, 4, 1 },
{ 1, 4, 1 },
{ 2, 5, 1 },
{ 3, 4, 1 },
{ 4, 1, 1 },
{ 5, 5, 1 },
{ 6, 6, 1 },
Annotation
- Immediate include surface: `amdgpu.h`, `amdgpu_pm.h`, `cikd.h`, `atom.h`, `amdgpu_atombios.h`, `amdgpu_dpm.h`, `kv_dpm.h`, `gfx_v7_0.h`.
- Detected declarations: `function kv_convert_vid2_to_vid7`, `function kv_convert_vid7_to_vid2`, `function sumo_take_smu_control`, `function sumo_construct_sclk_voltage_mapping_table`, `function sumo_construct_vid_mapping_table`, `function kv_program_local_cac_table`, `function kv_program_pt_config_registers`, `function kv_do_enable_didt`, `function kv_enable_didt`, `function kv_initialize_hardware_cac_manager`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.