drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
Extension
.c
Size
7391 bytes
Lines
302
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

while (byte_count > 0) {
			/* SMC address space is BE */
			data = (data << 8) + *src++;
			byte_count--;
		}

		data <<= extra_shift;
		data |= (original_data & ~((~0UL) << extra_shift));

		ret = si_set_smc_sram_address(adev, addr, limit);
		if (ret)
			goto done;

		WREG32(mmSMC_IND_DATA_0, data);
	}

done:
	spin_unlock_irqrestore(&adev->reg.smc.lock, flags);

	return ret;
}

void amdgpu_si_start_smc(struct amdgpu_device *adev)
{
	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

	tmp &= ~RST_REG;

	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
}

void amdgpu_si_reset_smc(struct amdgpu_device *adev)
{
	u32 tmp;

	RREG32(mmCB_CGTT_SCLK_CTRL);
	RREG32(mmCB_CGTT_SCLK_CTRL);
	RREG32(mmCB_CGTT_SCLK_CTRL);
	RREG32(mmCB_CGTT_SCLK_CTRL);

	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
	      RST_REG;
	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
}

int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev)
{
	static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };

	return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
}

void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)
{
	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

	if (enable)
		tmp &= ~CK_DISABLE;
	else
		tmp |= CK_DISABLE;

	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
}

bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
{
	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

	if (!(rst & RST_REG) && !(clk & CK_DISABLE))
		return true;

	return false;
}

PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev,
				       PPSMC_Msg msg)
{
	u32 tmp;
	int i;
	int usec_timeout;

	/* SMC seems to process some messages exceptionally slowly. */
	switch (msg) {
	case PPSMC_MSG_NoForcedLevel:
	case PPSMC_MSG_SetEnabledLevels:
	case PPSMC_MSG_SetForcedLevels:
	case PPSMC_MSG_DisableULV:
	case PPSMC_MSG_SwitchToSwState:
		usec_timeout = 1000000; /* 1 sec */

Annotation

Implementation Notes