drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c- Extension
.c- Size
- 39487 bytes
- Lines
- 1612
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/kernel.hlinux/gfp.hlinux/slab.hlinux/firmware.hlinux/reboot.hamd_shared.hpower_state.hamdgpu.hhwmgr.hamdgpu_dpm_internal.h
Detected Declarations
function amd_powerplay_createfunction amd_powerplay_destroyfunction pp_early_initfunction pp_swctf_delayed_work_handlerfunction pp_sw_initfunction pp_sw_finifunction pp_hw_initfunction pp_hw_finifunction pp_reserve_vram_for_smufunction pp_late_initfunction pp_late_finifunction pp_is_idlefunction pp_set_powergating_statefunction pp_suspendfunction pp_resumefunction pp_set_clockgating_statefunction pp_dpm_load_fwfunction pp_dpm_fw_loading_completefunction pp_set_clockgating_by_smufunction pp_dpm_en_umd_pstatefunction pp_dpm_force_performance_levelfunction pp_dpm_get_performance_levelfunction pp_dpm_get_sclkfunction pp_dpm_get_mclkfunction pp_dpm_powergate_vcefunction pp_dpm_powergate_uvdfunction pp_dpm_dispatch_tasksfunction pp_dpm_get_current_power_statefunction pp_dpm_set_fan_control_modefunction pp_dpm_get_fan_control_modefunction pp_dpm_set_fan_speed_pwmfunction pp_dpm_get_fan_speed_pwmfunction pp_dpm_get_fan_speed_rpmfunction pp_dpm_set_fan_speed_rpmfunction pp_dpm_get_pp_num_statesfunction pp_dpm_get_pp_tablefunction amd_powerplay_resetfunction pp_dpm_set_pp_tablefunction pp_dpm_force_clock_levelfunction pp_dpm_emit_clock_levelsfunction pp_dpm_get_sclk_odfunction pp_dpm_set_sclk_odfunction pp_dpm_get_mclk_odfunction pp_dpm_set_mclk_odfunction pp_dpm_read_sensorfunction pp_dpm_get_vce_clock_statefunction pp_get_power_profile_modefunction pp_set_power_profile_mode
Annotated Snippet
if (*level & profile_mode_mask) {
hwmgr->saved_dpm_level = hwmgr->dpm_level;
hwmgr->en_umd_pstate = true;
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
if (!(*level & profile_mode_mask)) {
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
*level = hwmgr->saved_dpm_level;
hwmgr->en_umd_pstate = false;
}
}
}
static int pp_dpm_force_performance_level(void *handle,
enum amd_dpm_forced_level level)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
if (level == hwmgr->dpm_level)
return 0;
pp_dpm_en_umd_pstate(hwmgr, &level);
hwmgr->request_dpm_level = level;
hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
return 0;
}
static enum amd_dpm_forced_level pp_dpm_get_performance_level(
void *handle)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
return hwmgr->dpm_level;
}
static uint32_t pp_dpm_get_sclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return 0;
if (hwmgr->hwmgr_func->get_sclk == NULL) {
pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
}
static uint32_t pp_dpm_get_mclk(void *handle, bool low)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return 0;
if (hwmgr->hwmgr_func->get_mclk == NULL) {
pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
}
static void pp_dpm_powergate_vce(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
return;
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
pr_info_ratelimited("%s was not implemented.\n", __func__);
return;
}
hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
}
static void pp_dpm_powergate_uvd(void *handle, bool gate)
{
struct pp_hwmgr *hwmgr = handle;
if (!hwmgr || !hwmgr->pm_en)
Annotation
- Immediate include surface: `linux/types.h`, `linux/kernel.h`, `linux/gfp.h`, `linux/slab.h`, `linux/firmware.h`, `linux/reboot.h`, `amd_shared.h`, `power_state.h`.
- Detected declarations: `function amd_powerplay_create`, `function amd_powerplay_destroy`, `function pp_early_init`, `function pp_swctf_delayed_work_handler`, `function pp_sw_init`, `function pp_sw_fini`, `function pp_hw_init`, `function pp_hw_fini`, `function pp_reserve_vram_for_smu`, `function pp_late_init`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.