drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
Extension
.h
Size
14234 bytes
Lines
351
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pp_atomctrl_clock_dividers {
	uint32_t pll_post_divider;
	uint32_t pll_feedback_divider;
	uint32_t pll_ref_divider;
	bool  enable_post_divider;
};

typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;

union pp_atomctrl_tcipll_fb_divider {
	struct {
		uint32_t ul_fb_div_frac : 14;
		uint32_t ul_fb_div : 12;
		uint32_t un_used : 6;
	};
	uint32_t ul_fb_divider;
};

typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;

struct pp_atomctrl_clock_dividers_rv730 {
	uint32_t pll_post_divider;
	pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
	uint32_t pll_ref_divider;
	bool  enable_post_divider;
	bool  enable_dithen;
	uint32_t vco_mode;
};
typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;


struct pp_atomctrl_clock_dividers_kong {
	uint32_t    pll_post_divider;
	uint32_t    real_clock;
};
typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;

struct pp_atomctrl_clock_dividers_ci {
	uint32_t    pll_post_divider;               /* post divider value */
	uint32_t    real_clock;
	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
	uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
	uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;

struct pp_atomctrl_clock_dividers_vi {
	uint32_t    pll_post_divider;               /* post divider value */
	uint32_t    real_clock;
	pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
	uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
	uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
	uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
};
typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;

struct pp_atomctrl_clock_dividers_ai {
	u16 usSclk_fcw_frac;
	u16  usSclk_fcw_int;
	u8   ucSclkPostDiv;
	u8   ucSclkVcoMode;
	u8   ucSclkPllRange;
	u8   ucSscEnable;
	u16  usSsc_fcw1_frac;
	u16  usSsc_fcw1_int;
	u16  usReserved;
	u16  usPcc_fcw_int;
	u16  usSsc_fcw_slew_frac;
	u16  usPcc_fcw_slew_frac;
};
typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;


union pp_atomctrl_s_mpll_fb_divider {
	struct {
		uint32_t cl_kf : 12;
		uint32_t clk_frac : 12;
		uint32_t un_used : 8;
	};
	uint32_t ul_fb_divider;
};
typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;

enum pp_atomctrl_spread_spectrum_mode {
	pp_atomctrl_spread_spectrum_mode_down = 0,
	pp_atomctrl_spread_spectrum_mode_center
};
typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;

Annotation

Implementation Notes