drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
Extension
.c
Size
61026 bytes
Lines
1805
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
		const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
			(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;

		if (powerplay_table3->usExtendendedHeaderOffset > 0) {
			const ATOM_PPLIB_EXTENDEDHEADER  *extended_header =
						(const ATOM_PPLIB_EXTENDEDHEADER *)
						(((unsigned long)powerplay_table3) +
						le16_to_cpu(powerplay_table3->usExtendendedHeaderOffset));
			if (le16_to_cpu(extended_header->usSize) >=
			   SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2)
				vce_table_offset = le16_to_cpu(extended_header->usVCETableOffset);
		}
	}

	return vce_table_offset;
}

static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,
			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_table_offset(hwmgr,
						powerplay_table);

	if (table_offset > 0)
		return table_offset + 1;

	return 0;
}

static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,
			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
							powerplay_table);
	uint16_t table_size = 0;

	if (table_offset > 0) {
		const VCEClockInfoArray *p = (const VCEClockInfoArray *)
			(((unsigned long) powerplay_table) + table_offset);
		table_size = sizeof(uint8_t) + p->ucNumEntries * sizeof(VCEClockInfo);
	}

	return table_size;
}

static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,
				const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
							powerplay_table);

	if (table_offset > 0)
		return table_offset + get_vce_clock_info_array_size(hwmgr,
							powerplay_table);

	return 0;
}

static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,
							const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
	uint16_t table_size = 0;

	if (table_offset > 0) {
		const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *ptable =
			(const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)(((unsigned long) powerplay_table) + table_offset);

		table_size = sizeof(uint8_t) + ptable->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record);
	}
	return table_size;
}

static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);

	if (table_offset > 0)
		return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);

	return 0;
}

static const ATOM_PPLIB_VCE_State_Table *get_vce_state_table(
						struct pp_hwmgr *hwmgr,
						const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
	uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);

Annotation

Implementation Notes