drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
Extension
.h
Size
9558 bytes
Lines
326
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu10_dpm_entry {
	uint32_t soft_min_clk;
	uint32_t hard_min_clk;
	uint32_t soft_max_clk;
	uint32_t hard_max_clk;
};

struct smu10_power_level {
	uint32_t engine_clock;
	uint8_t vddc_index;
	uint8_t ds_divider_index;
	uint8_t ss_divider_index;
	uint8_t allow_gnb_slow;
	uint8_t force_nbp_state;
	uint8_t display_wm;
	uint8_t vce_wm;
	uint8_t num_simd_to_powerdown;
	uint8_t hysteresis_up;
	uint8_t rsv[3];
};

/*used for the nbpsFlags field in smu10_power state*/
#define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)

#define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE    (1<<0)

struct smu10_uvd_clocks {
	uint32_t vclk;
	uint32_t dclk;
	uint32_t vclk_low_divider;
	uint32_t vclk_high_divider;
	uint32_t dclk_low_divider;
	uint32_t dclk_high_divider;
};

struct pp_disable_nbpslo_flags {
	union {
		struct {
			uint32_t entry : 1;
			uint32_t display : 1;
			uint32_t driver: 1;
			uint32_t vce : 1;
			uint32_t uvd : 1;
			uint32_t acp : 1;
			uint32_t reserved: 26;
		} bits;
		uint32_t u32All;
	};
};


enum smu10_pstate_previous_action {
	DO_NOTHING = 1,
	FORCE_HIGH,
	CANCEL_FORCE_HIGH
};

struct smu10_power_state {
	unsigned int magic;
	uint32_t level;
	struct smu10_uvd_clocks uvd_clocks;
	uint32_t evclk;
	uint32_t ecclk;
	uint32_t samclk;
	uint32_t acpclk;
	bool need_dfs_bypass;

	uint32_t nbps_flags;
	uint32_t bapm_flags;
	uint8_t dpm0_pg_nbps_low;
	uint8_t dpm0_pg_nbps_high;
	uint8_t dpm_x_nbps_low;
	uint8_t dpm_x_nbps_high;

	enum smu10_pstate_previous_action action;

	struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
	struct pp_disable_nbpslo_flags nbpslo_flags;
};

#define SMU10_NUM_NBPSTATES        4
#define SMU10_NUM_NBPMEMORYCLOCK   2


struct smu10_display_phy_info_entry {
	uint8_t                   phy_present;
	uint8_t                   active_lane_mapping;
	uint8_t                   display_config_type;

Annotation

Implementation Notes