drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
Extension
.h
Size
13245 bytes
Lines
390
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct gpu_pt_config_reg {
	uint32_t                           offset;
	uint32_t                           mask;
	uint32_t                           shift;
	uint32_t                           value;
	enum gpu_pt_config_reg_type       type;
};

struct smu7_performance_level {
	uint32_t  memory_clock;
	uint32_t  engine_clock;
	uint16_t  pcie_gen;
	uint16_t  pcie_lane;
};

struct smu7_thermal_temperature_setting {
	long temperature_low;
	long temperature_high;
	long temperature_shutdown;
};

struct smu7_uvd_clocks {
	uint32_t  vclk;
	uint32_t  dclk;
};

struct smu7_vce_clocks {
	uint32_t  evclk;
	uint32_t  ecclk;
};

struct smu7_power_state {
	uint32_t                  magic;
	struct smu7_uvd_clocks    uvd_clks;
	struct smu7_vce_clocks    vce_clks;
	uint32_t                  sam_clk;
	uint16_t                  performance_level_count;
	bool                      dc_compatible;
	uint32_t                  sclk_threshold;
	struct smu7_performance_level  performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
};

struct smu7_dpm_level {
	bool	enabled;
	uint32_t	value;
	uint32_t	param1;
};

#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 8
#define SMU7_MINIMUM_ENGINE_CLOCK 2500

struct smu7_single_dpm_table {
	uint32_t		count;
	struct smu7_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
};

struct smu7_dpm_table {
	struct smu7_single_dpm_table  sclk_table;
	struct smu7_single_dpm_table  mclk_table;
	struct smu7_single_dpm_table  pcie_speed_table;
	struct smu7_single_dpm_table  vddc_table;
	struct smu7_single_dpm_table  vddci_table;
	struct smu7_single_dpm_table  mvdd_table;
};

struct smu7_clock_registers {
	uint32_t  vCG_SPLL_FUNC_CNTL;
	uint32_t  vCG_SPLL_FUNC_CNTL_2;
	uint32_t  vCG_SPLL_FUNC_CNTL_3;
	uint32_t  vCG_SPLL_FUNC_CNTL_4;
	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
	uint32_t  vDLL_CNTL;
	uint32_t  vMCLK_PWRMGT_CNTL;
	uint32_t  vMPLL_AD_FUNC_CNTL;
	uint32_t  vMPLL_DQ_FUNC_CNTL;
	uint32_t  vMPLL_FUNC_CNTL;
	uint32_t  vMPLL_FUNC_CNTL_1;
	uint32_t  vMPLL_FUNC_CNTL_2;
	uint32_t  vMPLL_SS1;
	uint32_t  vMPLL_SS2;
};

#define DISABLE_MC_LOADMICROCODE   1
#define DISABLE_MC_CFGPROGRAMMING  2

struct smu7_voltage_smio_registers {
	uint32_t vS0_VID_LOWER_SMIO_CNTL;
};

Annotation

Implementation Notes