drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.h
Extension: .h
Size: 2841 bytes
Lines: 63
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _SMU7_POWERTUNE_H
#define _SMU7_POWERTUNE_H

#define DIDT_SQ_CTRL0__UNUSED_0_MASK    0xfffc0000
#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT  0x12
#define DIDT_TD_CTRL0__UNUSED_0_MASK    0xfffc0000
#define DIDT_TD_CTRL0__UNUSED_0__SHIFT  0x12
#define DIDT_TCP_CTRL0__UNUSED_0_MASK   0xfffc0000
#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
#define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK                 0xc0000000
#define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT               0x0000001e
#define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK                 0xc0000000
#define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT               0x0000001e
#define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK                0xc0000000
#define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT              0x0000001e

/* PowerContainment Features */
#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004

#define ixGC_CAC_CNTL 0x0000
#define ixDIDT_SQ_STALL_CTRL 0x0004
#define ixDIDT_SQ_TUNING_CTRL 0x0005
#define ixDIDT_TD_STALL_CTRL 0x0044
#define ixDIDT_TD_TUNING_CTRL 0x0045
#define ixDIDT_TCP_STALL_CTRL 0x0064
#define ixDIDT_TCP_TUNING_CTRL 0x0065


int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr);
int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr);
int smu7_enable_power_containment(struct pp_hwmgr *hwmgr);
int smu7_disable_power_containment(struct pp_hwmgr *hwmgr);
int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int smu7_power_control_set_level(struct pp_hwmgr *hwmgr);
int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);
int smu7_disable_didt_config(struct pp_hwmgr *hwmgr);
#endif  /* DGPU_POWERTUNE_H */

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.