drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h
Extension
.h
Size
8332 bytes
Lines
312
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu8_dpm_entry {
	uint32_t soft_min_clk;
	uint32_t hard_min_clk;
	uint32_t soft_max_clk;
	uint32_t hard_max_clk;
};

struct smu8_sys_info {
	uint32_t bootup_uma_clock;
	uint32_t bootup_engine_clock;
	uint32_t dentist_vco_freq;
	uint32_t nb_dpm_enable;
	uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
	uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
	uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
	uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
	uint16_t bootup_nb_voltage_index;
	uint8_t htc_tmp_lmt;
	uint8_t htc_hyst_lmt;
	uint32_t system_config;
	uint32_t uma_channel_number;
};

#define MAX_DISPLAYPHY_IDS			0x8
#define DISPLAYPHY_LANEMASK			0xF
#define UNKNOWN_TRANSMITTER_PHY_ID		(-1)

#define DISPLAYPHY_PHYID_SHIFT			24
#define DISPLAYPHY_LANESELECT_SHIFT		16

#define DISPLAYPHY_RX_SELECT			0x1
#define DISPLAYPHY_TX_SELECT			0x2
#define DISPLAYPHY_CORE_SELECT			0x4

#define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
		(((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
		((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
		((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
		((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
		((core) ? DISPLAYPHY_CORE_SELECT : 0))

struct smu8_display_phy_info_entry {
	uint8_t phy_present;
	uint8_t active_lane_mapping;
	uint8_t display_config_type;
	uint8_t active_number_of_lanes;
};

#define SMU8_MAX_DISPLAYPHY_IDS			10

struct smu8_display_phy_info {
	bool display_phy_access_initialized;
	struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
};

struct smu8_power_level {
	uint32_t engineClock;
	uint8_t vddcIndex;
	uint8_t dsDividerIndex;
	uint8_t ssDividerIndex;
	uint8_t allowGnbSlow;
	uint8_t forceNBPstate;
	uint8_t display_wm;
	uint8_t vce_wm;
	uint8_t numSIMDToPowerDown;
	uint8_t hysteresis_up;
	uint8_t rsv[3];
};

struct smu8_uvd_clocks {
	uint32_t vclk;
	uint32_t dclk;
	uint32_t vclk_low_divider;
	uint32_t vclk_high_divider;
	uint32_t dclk_low_divider;
	uint32_t dclk_high_divider;
};

enum smu8_pstate_previous_action {
	DO_NOTHING = 1,
	FORCE_HIGH,
	CANCEL_FORCE_HIGH
};

struct pp_disable_nb_ps_flags {
	union {
		struct {
			uint32_t entry : 1;
			uint32_t display : 1;
			uint32_t driver: 1;

Annotation

Implementation Notes