drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h
Extension
.h
Size
14179 bytes
Lines
448
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu_features {
	bool supported;
	bool enabled;
	uint32_t smu_feature_id;
	uint32_t smu_feature_bitmap;
};

struct vega10_performance_level {
	uint32_t  soc_clock;
	uint32_t  gfx_clock;
	uint32_t  mem_clock;
};

struct vega10_bacos {
	uint32_t                       baco_flags;
	/* struct vega10_performance_level  performance_level; */
};

struct vega10_uvd_clocks {
	uint32_t  vclk;
	uint32_t  dclk;
};

struct vega10_vce_clocks {
	uint32_t  evclk;
	uint32_t  ecclk;
};

struct vega10_power_state {
	uint32_t                  magic;
	struct vega10_uvd_clocks    uvd_clks;
	struct vega10_vce_clocks    vce_clks;
	uint16_t                  performance_level_count;
	bool                      dc_compatible;
	uint32_t                  sclk_threshold;
	struct vega10_performance_level  performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS];
};

struct vega10_dpm_level {
	bool	enabled;
	uint32_t	value;
	uint32_t	param1;
};

#define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 8
#define MAX_PCIE_CONF 2
#define VEGA10_MINIMUM_ENGINE_CLOCK 2500

struct vega10_dpm_state {
	uint32_t  soft_min_level;
	uint32_t  soft_max_level;
	uint32_t  hard_min_level;
	uint32_t  hard_max_level;
};

struct vega10_single_dpm_table {
	uint32_t		count;
	struct vega10_dpm_state	dpm_state;
	struct vega10_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
};

struct vega10_pcie_table {
	uint16_t count;
	uint8_t  pcie_gen[MAX_PCIE_CONF];
	uint8_t  pcie_lane[MAX_PCIE_CONF];
	uint32_t lclk[MAX_PCIE_CONF];
};

struct vega10_dpm_table {
	struct vega10_single_dpm_table  soc_table;
	struct vega10_single_dpm_table  gfx_table;
	struct vega10_single_dpm_table  mem_table;
	struct vega10_single_dpm_table  eclk_table;
	struct vega10_single_dpm_table  vclk_table;
	struct vega10_single_dpm_table  dclk_table;
	struct vega10_single_dpm_table  dcef_table;
	struct vega10_single_dpm_table  pixel_table;
	struct vega10_single_dpm_table  display_table;
	struct vega10_single_dpm_table  phy_table;
	struct vega10_pcie_table        pcie_table;
};

#define VEGA10_MAX_LEAKAGE_COUNT  8
struct vega10_leakage_voltage {
	uint16_t  count;
	uint16_t  leakage_id[VEGA10_MAX_LEAKAGE_COUNT];
	uint16_t  actual_voltage[VEGA10_MAX_LEAKAGE_COUNT];
};

Annotation

Implementation Notes