drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h
Extension: .h
Size: 2922 bytes
Lines: 83
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct vega10_pt_config_reg
struct vega10_didt_config_reg
struct vega10_pt_defaults
enum vega10_pt_config_reg_type
enum vega10_didt_config_reg_type

Annotated Snippet

struct vega10_pt_config_reg {
	uint32_t                           offset;
	uint32_t                           mask;
	uint32_t                           shift;
	uint32_t                           value;
	enum vega10_pt_config_reg_type       type;
};

struct vega10_didt_config_reg {
	uint32_t		offset;
	uint32_t		mask;
	uint32_t		shift;
	uint32_t		value;
};

struct vega10_pt_defaults {
    uint8_t   SviLoadLineEn;
    uint8_t   SviLoadLineVddC;
    uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
    uint8_t   TDC_MAWt;
    uint8_t   TdcWaterfallCtl;
    uint8_t   DTEAmbientTempBase;
};

void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);

int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);

#endif  /* _VEGA10_POWERTUNE_H_ */

Annotation

Detected declarations: `struct vega10_pt_config_reg`, `struct vega10_didt_config_reg`, `struct vega10_pt_defaults`, `enum vega10_pt_config_reg_type`, `enum vega10_didt_config_reg_type`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.