drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h- Extension
.h- Size
- 18254 bytes
- Lines
- 440
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _VEGA10_PPTABLE_H_
#define _VEGA10_PPTABLE_H_
#pragma pack(push, 1)
#define ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
#define ATOM_VEGA10_PP_FANPARAMETERS_NOFAN 0x80
#define ATOM_VEGA10_PP_THERMALCONTROLLER_NONE 0
#define ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163 17
#define ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 24
#define ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89
#define ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D
#define ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY 0x1
#define ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
#define ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC 0x4
#define ATOM_VEGA10_PP_PLATFORM_CAP_BACO 0x8
#define ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x10
/* ATOM_PPLIB_NONCLOCK_INFO::usClassification */
#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
/* 2, 4, 6, 7 are reserved */
#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
/* ATOM_PPLIB_NONCLOCK_INFO::usClassification2 */
#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
#define ATOM_Vega10_DISALLOW_ON_DC 0x00004000
#define ATOM_Vega10_ENABLE_VARIBRIGHT 0x00008000
#define ATOM_Vega10_TABLE_REVISION_VEGA10 8
#define ATOM_Vega10_VoltageMode_AVFS_Interpolate 0
#define ATOM_Vega10_VoltageMode_AVFS_WorstCase 1
#define ATOM_Vega10_VoltageMode_Static 2
typedef struct _ATOM_Vega10_POWERPLAYTABLE {
struct atom_common_table_header sHeader;
UCHAR ucTableRevision;
USHORT usTableSize; /* the size of header structure */
ULONG ulGoldenPPID; /* PPGen use only */
ULONG ulGoldenRevision; /* PPGen use only */
USHORT usFormatID; /* PPGen use only */
ULONG ulPlatformCaps; /* See ATOM_Vega10_CAPS_* */
ULONG ulMaxODEngineClock; /* For Overdrive. */
ULONG ulMaxODMemoryClock; /* For Overdrive. */
USHORT usPowerControlLimit;
USHORT usUlvVoltageOffset; /* in mv units */
USHORT usUlvSmnclkDid;
USHORT usUlvMp1clkDid;
USHORT usUlvGfxclkBypass;
USHORT usGfxclkSlewRate;
UCHAR ucGfxVoltageMode;
UCHAR ucSocVoltageMode;
UCHAR ucUclkVoltageMode;
UCHAR ucUvdVoltageMode;
UCHAR ucVceVoltageMode;
UCHAR ucMp0VoltageMode;
UCHAR ucDcefVoltageMode;
USHORT usStateArrayOffset; /* points to ATOM_Vega10_State_Array */
USHORT usFanTableOffset; /* points to ATOM_Vega10_Fan_Table */
USHORT usThermalControllerOffset; /* points to ATOM_Vega10_Thermal_Controller */
USHORT usSocclkDependencyTableOffset; /* points to ATOM_Vega10_SOCCLK_Dependency_Table */
USHORT usMclkDependencyTableOffset; /* points to ATOM_Vega10_MCLK_Dependency_Table */
USHORT usGfxclkDependencyTableOffset; /* points to ATOM_Vega10_GFXCLK_Dependency_Table */
USHORT usDcefclkDependencyTableOffset; /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */
USHORT usVddcLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
USHORT usVddmemLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
USHORT usMMDependencyTableOffset; /* points to ATOM_Vega10_MM_Dependency_Table */
USHORT usVCEStateTableOffset; /* points to ATOM_Vega10_VCE_State_Table */
USHORT usReserve; /* No PPM Support for Vega10 */
USHORT usPowerTuneTableOffset; /* points to ATOM_Vega10_PowerTune_Table */
USHORT usHardLimitTableOffset; /* points to ATOM_Vega10_Hard_Limit_Table */
USHORT usVddciLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
USHORT usPCIETableOffset; /* points to ATOM_Vega10_PCIE_Table */
USHORT usPixclkDependencyTableOffset; /* points to ATOM_Vega10_PIXCLK_Dependency_Table */
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.