drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h
Extension
.h
Size
14534 bytes
Lines
458
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu_features {
	bool supported;
	bool enabled;
	bool allowed;
	uint32_t smu_feature_id;
	uint64_t smu_feature_bitmap;
};

struct vega12_dpm_level {
	bool		enabled;
	uint32_t	value;
	uint32_t	param1;
};

#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
#define VEGA12_MINIMUM_ENGINE_CLOCK 2500

struct vega12_dpm_state {
	uint32_t  soft_min_level;
	uint32_t  soft_max_level;
	uint32_t  hard_min_level;
	uint32_t  hard_max_level;
};

struct vega12_single_dpm_table {
	uint32_t		count;
	struct vega12_dpm_state	dpm_state;
	struct vega12_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
};

struct vega12_odn_dpm_control {
	uint32_t	count;
	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
};

struct vega12_pcie_table {
	uint16_t count;
	uint8_t  pcie_gen[MAX_PCIE_CONF];
	uint8_t  pcie_lane[MAX_PCIE_CONF];
	uint32_t lclk[MAX_PCIE_CONF];
};

struct vega12_dpm_table {
	struct vega12_single_dpm_table  soc_table;
	struct vega12_single_dpm_table  gfx_table;
	struct vega12_single_dpm_table  mem_table;
	struct vega12_single_dpm_table  eclk_table;
	struct vega12_single_dpm_table  vclk_table;
	struct vega12_single_dpm_table  dclk_table;
	struct vega12_single_dpm_table  dcef_table;
	struct vega12_single_dpm_table  pixel_table;
	struct vega12_single_dpm_table  display_table;
	struct vega12_single_dpm_table  phy_table;
	struct vega12_pcie_table        pcie_table;
};

#define VEGA12_MAX_LEAKAGE_COUNT  8
struct vega12_leakage_voltage {
	uint16_t  count;
	uint16_t  leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
	uint16_t  actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
};

struct vega12_display_timing {
	uint32_t  min_clock_in_sr;
	uint32_t  num_existing_displays;
};

struct vega12_dpmlevel_enable_mask {
	uint32_t  uvd_dpm_enable_mask;
	uint32_t  vce_dpm_enable_mask;
	uint32_t  samu_dpm_enable_mask;
	uint32_t  sclk_dpm_enable_mask;
	uint32_t  mclk_dpm_enable_mask;
};

struct vega12_vbios_boot_state {
	bool        bsoc_vddc_lock;
	uint8_t     uc_cooling_id;
	uint16_t    vddc;
	uint16_t    vddci;
	uint16_t    mvddc;
	uint16_t    vdd_gfx;
	uint32_t    gfx_clock;
	uint32_t    mem_clock;
	uint32_t    soc_clock;
	uint32_t    dcef_clock;
	uint32_t    eclock;

Annotation

Implementation Notes