drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_pptable.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_pptable.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_pptable.h- Extension
.h- Size
- 3813 bytes
- Lines
- 109
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum ATOM_VEGA12_ODSETTING_IDenum ATOM_VEGA12_PPCLOCK_ID
Annotated Snippet
#ifndef _VEGA12_PPTABLE_H_
#define _VEGA12_PPTABLE_H_
#pragma pack(push, 1)
#define ATOM_VEGA12_PP_THERMALCONTROLLER_NONE 0
#define ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12 25
#define ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY 0x1
#define ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
#define ATOM_VEGA12_PP_PLATFORM_CAP_HARDWAREDC 0x4
#define ATOM_VEGA12_PP_PLATFORM_CAP_BACO 0x8
#define ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO 0x10
#define ATOM_VEGA12_PP_PLATFORM_CAP_ENABLESHADOWPSTATE 0x20
#define ATOM_VEGA12_TABLE_REVISION_VEGA12 9
enum ATOM_VEGA12_ODSETTING_ID {
ATOM_VEGA12_ODSETTING_GFXCLKFMAX = 0,
ATOM_VEGA12_ODSETTING_GFXCLKFMIN,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P1,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P2,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P3,
ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3,
ATOM_VEGA12_ODSETTING_UCLKFMAX,
ATOM_VEGA12_ODSETTING_POWERPERCENTAGE,
ATOM_VEGA12_ODSETTING_FANRPMMIN,
ATOM_VEGA12_ODSETTING_FANRPMACOUSTICLIMIT,
ATOM_VEGA12_ODSETTING_FANTARGETTEMPERATURE,
ATOM_VEGA12_ODSETTING_OPERATINGTEMPMAX,
ATOM_VEGA12_ODSETTING_COUNT,
};
typedef enum ATOM_VEGA12_ODSETTING_ID ATOM_VEGA12_ODSETTING_ID;
enum ATOM_VEGA12_PPCLOCK_ID {
ATOM_VEGA12_PPCLOCK_GFXCLK = 0,
ATOM_VEGA12_PPCLOCK_VCLK,
ATOM_VEGA12_PPCLOCK_DCLK,
ATOM_VEGA12_PPCLOCK_ECLK,
ATOM_VEGA12_PPCLOCK_SOCCLK,
ATOM_VEGA12_PPCLOCK_UCLK,
ATOM_VEGA12_PPCLOCK_DCEFCLK,
ATOM_VEGA12_PPCLOCK_DISPCLK,
ATOM_VEGA12_PPCLOCK_PIXCLK,
ATOM_VEGA12_PPCLOCK_PHYCLK,
ATOM_VEGA12_PPCLOCK_COUNT,
};
typedef enum ATOM_VEGA12_PPCLOCK_ID ATOM_VEGA12_PPCLOCK_ID;
typedef struct _ATOM_VEGA12_POWERPLAYTABLE {
struct atom_common_table_header sHeader;
UCHAR ucTableRevision;
USHORT usTableSize;
ULONG ulGoldenPPID;
ULONG ulGoldenRevision;
USHORT usFormatID;
ULONG ulPlatformCaps;
UCHAR ucThermalControllerType;
USHORT usSmallPowerLimit1;
USHORT usSmallPowerLimit2;
USHORT usBoostPowerLimit;
USHORT usODTurboPowerLimit;
USHORT usODPowerSavePowerLimit;
USHORT usSoftwareShutdownTemp;
ULONG PowerSavingClockMax[ATOM_VEGA12_PPCLOCK_COUNT];
ULONG PowerSavingClockMin[ATOM_VEGA12_PPCLOCK_COUNT];
ULONG ODSettingsMax[ATOM_VEGA12_ODSETTING_COUNT];
ULONG ODSettingsMin[ATOM_VEGA12_ODSETTING_COUNT];
USHORT usReserve[5];
PPTable_t smcPPTable;
} ATOM_Vega12_POWERPLAYTABLE;
#pragma pack(pop)
#endif
Annotation
- Detected declarations: `enum ATOM_VEGA12_ODSETTING_ID`, `enum ATOM_VEGA12_PPCLOCK_ID`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.