drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c- Extension
.c- Size
- 144631 bytes
- Lines
- 4493
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/module.hlinux/slab.hhwmgr.hamd_powerplay.hvega20_smumgr.hhardwaremanager.hppatomfwctrl.hatomfirmware.hcgs_common.hvega20_powertune.hvega20_inc.hpppcielanes.hvega20_hwmgr.hvega20_processpptables.hvega20_pptable.hvega20_thermal.hvega20_ppsmc.hpp_debug.hamd_pcie_helpers.hppinterrupt.hpp_overdriver.hpp_thermal.hsoc15_common.hvega20_baco.hsmuio/smuio_9_0_offset.hsmuio/smuio_9_0_sh_mask.hnbio/nbio_7_4_sh_mask.h
Detected Declarations
function vega20_set_default_registry_datafunction vega20_set_features_platform_capsfunction vega20_init_dpm_defaultsfunction vega20_set_private_data_based_on_pptablefunction vega20_hwmgr_backend_finifunction vega20_hwmgr_backend_initfunction vega20_init_sclk_thresholdfunction vega20_setup_asic_taskfunction vega20_init_dpm_statefunction vega20_get_number_of_dpm_levelfunction vega20_get_dpm_frequency_by_indexfunction vega20_setup_single_dpm_tablefunction vega20_setup_gfxclk_dpm_tablefunction vega20_setup_memclk_dpm_tablefunction vega20_setup_default_dpm_tablesfunction vega20_init_smc_tablefunction vega20_override_pcie_parametersfunction vega20_set_allowed_featuresmaskfunction vega20_run_btcfunction vega20_run_btc_afllfunction vega20_enable_all_smu_featuresfunction vega20_notify_smc_display_changefunction vega20_send_clock_ratiofunction vega20_disable_all_smu_featuresfunction vega20_od8_set_feature_capabilitiesfunction vega20_od8_set_feature_idfunction vega20_od8_get_gfx_clock_base_voltagefunction vega20_od8_initialize_default_settingsfunction vega20_od8_set_settingsfunction vega20_get_sclk_odfunction vega20_set_sclk_odfunction vega20_get_mclk_odfunction vega20_set_mclk_odfunction vega20_populate_umdpstate_clocksfunction vega20_get_max_sustainable_clockfunction vega20_init_max_sustainable_clocksfunction vega20_enable_mgpu_fan_boostfunction vega20_init_powergate_statefunction vega20_enable_dpm_tasksfunction vega20_find_lowest_dpm_levelfunction vega20_find_highest_dpm_levelfunction vega20_upload_dpm_min_levelfunction vega20_upload_dpm_max_levelfunction vega20_enable_disable_vce_dpmfunction vega20_get_clock_rangesfunction vega20_dpm_get_sclkfunction vega20_dpm_get_mclkfunction vega20_get_metrics_table
Annotated Snippet
if (od8_settings->od8_settings_array[i].feature_id) {
od8_settings->od8_settings_array[i].min_value =
pptable_information->od_settings_min[i];
od8_settings->od8_settings_array[i].max_value =
pptable_information->od_settings_max[i];
od8_settings->od8_settings_array[i].current_value =
od8_settings->od8_settings_array[i].default_value;
} else {
od8_settings->od8_settings_array[i].min_value =
0;
od8_settings->od8_settings_array[i].max_value =
0;
od8_settings->od8_settings_array[i].current_value =
0;
}
}
ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
PP_ASSERT_WITH_CODE(!ret,
"Failed to import over drive table!",
return ret);
return 0;
}
static int vega20_od8_set_settings(
struct pp_hwmgr *hwmgr,
uint32_t index,
uint32_t value)
{
OverDriveTable_t od_table;
int ret = 0;
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
struct vega20_od8_single_setting *od8_settings =
data->od8_settings.od8_settings_array;
ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export over drive table!",
return ret);
switch (index) {
case OD8_SETTING_GFXCLK_FMIN:
od_table.GfxclkFmin = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_FMAX:
if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
return -EINVAL;
od_table.GfxclkFmax = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_FREQ1:
od_table.GfxclkFreq1 = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_VOLTAGE1:
od_table.GfxclkVolt1 = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_FREQ2:
od_table.GfxclkFreq2 = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_VOLTAGE2:
od_table.GfxclkVolt2 = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_FREQ3:
od_table.GfxclkFreq3 = (uint16_t)value;
break;
case OD8_SETTING_GFXCLK_VOLTAGE3:
od_table.GfxclkVolt3 = (uint16_t)value;
break;
case OD8_SETTING_UCLK_FMAX:
if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
return -EINVAL;
od_table.UclkFmax = (uint16_t)value;
break;
case OD8_SETTING_POWER_PERCENTAGE:
od_table.OverDrivePct = (int16_t)value;
break;
case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
od_table.FanMaximumRpm = (uint16_t)value;
break;
case OD8_SETTING_FAN_MIN_SPEED:
od_table.FanMinimumPwm = (uint16_t)value;
break;
case OD8_SETTING_FAN_TARGET_TEMP:
od_table.FanTargetTemperature = (uint16_t)value;
break;
case OD8_SETTING_OPERATING_TEMP_MAX:
od_table.MaxOpTemp = (uint16_t)value;
Annotation
- Immediate include surface: `linux/delay.h`, `linux/module.h`, `linux/slab.h`, `hwmgr.h`, `amd_powerplay.h`, `vega20_smumgr.h`, `hardwaremanager.h`, `ppatomfwctrl.h`.
- Detected declarations: `function vega20_set_default_registry_data`, `function vega20_set_features_platform_caps`, `function vega20_init_dpm_defaults`, `function vega20_set_private_data_based_on_pptable`, `function vega20_hwmgr_backend_fini`, `function vega20_hwmgr_backend_init`, `function vega20_init_sclk_threshold`, `function vega20_setup_asic_task`, `function vega20_init_dpm_state`, `function vega20_get_number_of_dpm_level`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.