drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h
Extension
.h
Size
18178 bytes
Lines
589
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu_features {
	bool supported;
	bool enabled;
	bool allowed;
	uint32_t smu_feature_id;
	uint64_t smu_feature_bitmap;
};

struct vega20_performance_level {
	uint32_t  soc_clock;
	uint32_t  gfx_clock;
	uint32_t  mem_clock;
};

struct vega20_bacos {
	uint32_t                       baco_flags;
	/* struct vega20_performance_level  performance_level; */
};

struct vega20_uvd_clocks {
	uint32_t  vclk;
	uint32_t  dclk;
};

struct vega20_vce_clocks {
	uint32_t  evclk;
	uint32_t  ecclk;
};

struct vega20_power_state {
	uint32_t                  magic;
	struct vega20_uvd_clocks    uvd_clks;
	struct vega20_vce_clocks    vce_clks;
	uint16_t                  performance_level_count;
	bool                      dc_compatible;
	uint32_t                  sclk_threshold;
	struct vega20_performance_level  performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS];
};

struct vega20_dpm_level {
	bool		enabled;
	uint32_t	value;
	uint32_t	param1;
};

#define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
#define VEGA20_MINIMUM_ENGINE_CLOCK 2500

struct vega20_max_sustainable_clocks {
	PP_Clock display_clock;
	PP_Clock phy_clock;
	PP_Clock pixel_clock;
	PP_Clock uclock;
	PP_Clock dcef_clock;
	PP_Clock soc_clock;
};

struct vega20_dpm_state {
	uint32_t  soft_min_level;
	uint32_t  soft_max_level;
	uint32_t  hard_min_level;
	uint32_t  hard_max_level;
};

struct vega20_single_dpm_table {
	uint32_t		count;
	struct vega20_dpm_state	dpm_state;
	struct vega20_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
};

struct vega20_odn_dpm_control {
	uint32_t	count;
	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
};

struct vega20_pcie_table {
	uint16_t count;
	uint8_t  pcie_gen[MAX_PCIE_CONF];
	uint8_t  pcie_lane[MAX_PCIE_CONF];
	uint32_t lclk[MAX_PCIE_CONF];
};

struct vega20_dpm_table {
	struct vega20_single_dpm_table  soc_table;
	struct vega20_single_dpm_table  gfx_table;
	struct vega20_single_dpm_table  mem_table;
	struct vega20_single_dpm_table  eclk_table;
	struct vega20_single_dpm_table  vclk_table;

Annotation

Implementation Notes