drivers/gpu/drm/amd/pm/powerplay/inc/amd_powerplay.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/pm/powerplay/inc/amd_powerplay.h

Extension

.h

Size

1427 bytes

Lines

36

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• linux/seq_file.h
• linux/types.h
• linux/errno.h
• amd_shared.h
• cgs_common.h
• dm_pp_interface.h
• kgd_pp_interface.h
• amdgpu.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _AMD_POWERPLAY_H_
#define _AMD_POWERPLAY_H_

#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/errno.h>
#include "amd_shared.h"
#include "cgs_common.h"
#include "dm_pp_interface.h"
#include "kgd_pp_interface.h"
#include "amdgpu.h"

#endif /* _AMD_POWERPLAY_H_ */

Annotation

• Immediate include surface: `linux/seq_file.h`, `linux/types.h`, `linux/errno.h`, `amd_shared.h`, `cgs_common.h`, `dm_pp_interface.h`, `kgd_pp_interface.h`, `amdgpu.h`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.