drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h- Extension
.h- Size
- 22950 bytes
- Lines
- 463
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct pp_hwmgrstruct pp_hw_power_statestruct pp_power_statestruct PP_TemperatureRangestruct phm_fan_speed_infostruct pp_hw_descriptorstruct PHM_PerformanceLevelstruct PP_Clocksstruct pp_clock_infostruct phm_platform_descriptorstruct phm_clocksstruct phm_odn_performance_levelstruct phm_odn_clock_levelsenum amd_dpm_forced_levelenum PHM_AutoThrottleSourceenum phm_platform_capsenum PHM_PerformanceLevelDesignationenum PP_PCIEGenenum phm_clock_Typefunction phm_cap_setfunction phm_cap_unsetfunction phm_cap_enabled
Annotated Snippet
struct phm_fan_speed_info {
uint32_t min_percent;
uint32_t max_percent;
uint32_t min_rpm;
uint32_t max_rpm;
bool supports_percent_read;
bool supports_percent_write;
bool supports_rpm_read;
bool supports_rpm_write;
};
/* Automatic Power State Throttling */
enum PHM_AutoThrottleSource {
PHM_AutoThrottleSource_Thermal,
PHM_AutoThrottleSource_External
};
typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
enum phm_platform_caps {
PHM_PlatformCaps_AtomBiosPpV1 = 0,
PHM_PlatformCaps_PowerPlaySupport,
PHM_PlatformCaps_ACOverdriveSupport,
PHM_PlatformCaps_BacklightSupport,
PHM_PlatformCaps_ThermalController,
PHM_PlatformCaps_BiosPowerSourceControl,
PHM_PlatformCaps_DisableVoltageTransition,
PHM_PlatformCaps_DisableEngineTransition,
PHM_PlatformCaps_DisableMemoryTransition,
PHM_PlatformCaps_DynamicPowerManagement,
PHM_PlatformCaps_EnableASPML0s,
PHM_PlatformCaps_EnableASPML1,
PHM_PlatformCaps_OD5inACSupport,
PHM_PlatformCaps_OD5inDCSupport,
PHM_PlatformCaps_SoftStateOD5,
PHM_PlatformCaps_NoOD5Support,
PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
PHM_PlatformCaps_ActivityReporting,
PHM_PlatformCaps_EnableBackbias,
PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
PHM_PlatformCaps_ShowPowerBudgetWarning,
PHM_PlatformCaps_PowerBudgetWaiverAvailable,
PHM_PlatformCaps_GFXClockGatingSupport,
PHM_PlatformCaps_MMClockGatingSupport,
PHM_PlatformCaps_AutomaticDCTransition,
PHM_PlatformCaps_GeminiPrimary,
PHM_PlatformCaps_MemorySpreadSpectrumSupport,
PHM_PlatformCaps_EngineSpreadSpectrumSupport,
PHM_PlatformCaps_StepVddc,
PHM_PlatformCaps_DynamicPCIEGen2Support,
PHM_PlatformCaps_SMC,
PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
PHM_PlatformCaps_ABM, /* ABM support.*/
PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
PHM_PlatformCaps_AdjustUVDPriorityForSP,
PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
Annotation
- Detected declarations: `struct pp_hwmgr`, `struct pp_hw_power_state`, `struct pp_power_state`, `struct PP_TemperatureRange`, `struct phm_fan_speed_info`, `struct pp_hw_descriptor`, `struct PHM_PerformanceLevel`, `struct PP_Clocks`, `struct pp_clock_info`, `struct phm_platform_descriptor`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.