drivers/gpu/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h
Extension: .h
Size: 148398 bytes
Lines: 1794
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct PWR_Command_Table
struct PWR_DFY_Section

Annotated Snippet

struct PWR_Command_Table {
	uint32_t              data;
	uint32_t reg;
};

typedef struct PWR_Command_Table PWR_Command_Table;

struct PWR_DFY_Section {
	uint32_t dfy_cntl;
	uint32_t dfy_addr_hi, dfy_addr_lo;
	uint32_t dfy_size;
	uint32_t dfy_data[];
};

typedef struct PWR_DFY_Section PWR_DFY_Section;

static const PWR_Command_Table pwr_virus_table_pre[] = {
	{ 0x00000000, mmRLC_CNTL                                 },
	{ 0x00000002, mmRLC_SRM_CNTL                             },
	{ 0x15000000, mmCP_ME_CNTL                               },
	{ 0x50000000, mmCP_MEC_CNTL                              },
	{ 0x80000004, mmCP_DFY_CNTL                              },
	{ 0x0840800a, mmCP_RB0_CNTL                              },
	{ 0xf30fff0f, mmTCC_CTRL                                 },
	{ 0x00000002, mmTCC_EXE_DISABLE                          },
	{ 0x000000ff, mmTCP_ADDR_CONFIG                          },
	{ 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
	{ 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
	{ 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
	{ 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },

Annotation

Detected declarations: `struct PWR_Command_Table`, `struct PWR_DFY_Section`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.