drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/power_state.h
Extension
.h
Size
5824 bytes
Lines
198
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pp_hw_power_state {
	unsigned int magic;
};

struct pp_power_state;


#define PP_INVALID_POWER_STATE_ID (0)


/*
 * An item of a list containing Power States.
 */

struct PP_StateLinkedList {
	struct pp_power_state *next;
	struct pp_power_state *prev;
};


enum PP_StateUILabel {
	PP_StateUILabel_None,
	PP_StateUILabel_Battery,
	PP_StateUILabel_MiddleLow,
	PP_StateUILabel_Balanced,
	PP_StateUILabel_MiddleHigh,
	PP_StateUILabel_Performance,
	PP_StateUILabel_BACO
};

enum PP_StateClassificationFlag {
	PP_StateClassificationFlag_Boot                = 0x0001,
	PP_StateClassificationFlag_Thermal             = 0x0002,
	PP_StateClassificationFlag_LimitedPowerSource  = 0x0004,
	PP_StateClassificationFlag_Rest                = 0x0008,
	PP_StateClassificationFlag_Forced              = 0x0010,
	PP_StateClassificationFlag_User3DPerformance   = 0x0020,
	PP_StateClassificationFlag_User2DPerformance   = 0x0040,
	PP_StateClassificationFlag_3DPerformance       = 0x0080,
	PP_StateClassificationFlag_ACOverdriveTemplate   = 0x0100,
	PP_StateClassificationFlag_Uvd                 = 0x0200,
	PP_StateClassificationFlag_3DPerformanceLow    = 0x0400,
	PP_StateClassificationFlag_ACPI                = 0x0800,
	PP_StateClassificationFlag_HD2                 = 0x1000,
	PP_StateClassificationFlag_UvdHD               = 0x2000,
	PP_StateClassificationFlag_UvdSD               = 0x4000,
	PP_StateClassificationFlag_UserDCPerformance    = 0x8000,
	PP_StateClassificationFlag_DCOverdriveTemplate   = 0x10000,
	PP_StateClassificationFlag_BACO                  = 0x20000,
	PP_StateClassificationFlag_LimitedPowerSource_2  = 0x40000,
	PP_StateClassificationFlag_ULV                   = 0x80000,
	PP_StateClassificationFlag_UvdMVC               = 0x100000,
};

typedef unsigned int PP_StateClassificationFlags;

struct PP_StateClassificationBlock {
	enum PP_StateUILabel         ui_label;
	enum PP_StateClassificationFlag  flags;
	int                          bios_index;
	bool                      temporary_state;
	bool                      to_be_deleted;
};

struct PP_StatePcieBlock {
	unsigned int lanes;
};

enum PP_RefreshrateSource {
	PP_RefreshrateSource_EDID,
	PP_RefreshrateSource_Explicit
};

struct PP_StateDisplayBlock {
	bool              disableFrameModulation;
	bool              limitRefreshrate;
	enum PP_RefreshrateSource refreshrateSource;
	int                  explicitRefreshrate;
	int                  edidRefreshrateIndex;
	bool              enableVariBright;
};

struct PP_StateMemroyBlock {
	bool              dllOff;
	uint8_t                 m3arb;
	uint8_t                 unused[3];
};

struct PP_StateSoftwareAlgorithmBlock {
	bool disableLoadBalancing;

Annotation

Implementation Notes