drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h
Extension
.h
Size
22427 bytes
Lines
784
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct SMIO_Pattern {
	uint16_t Voltage;
	uint8_t  Smio;
	uint8_t  padding;
};

typedef struct SMIO_Pattern SMIO_Pattern;

struct SMIO_Table {
	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};

typedef struct SMIO_Table SMIO_Table;

struct SMU72_Discrete_GraphicsLevel {
	SMU_VoltageLevel MinVoltage;

	uint32_t    SclkFrequency;

	uint8_t     pcieDpmLevel;
	uint8_t     DeepSleepDivId;
	uint16_t    ActivityLevel;

	uint32_t    CgSpllFuncCntl3;
	uint32_t    CgSpllFuncCntl4;
	uint32_t    SpllSpreadSpectrum;
	uint32_t    SpllSpreadSpectrum2;
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;
	uint8_t     SclkDid;
	uint8_t     DisplayWatermark;
	uint8_t     EnabledForActivity;
	uint8_t     EnabledForThrottle;
	uint8_t     UpHyst;
	uint8_t     DownHyst;
	uint8_t     VoltageDownHyst;
	uint8_t     PowerThrottle;
};

typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;

struct SMU72_Discrete_ACPILevel {
	uint32_t    Flags;
	SMU_VoltageLevel MinVoltage;
	uint32_t    SclkFrequency;
	uint8_t     SclkDid;
	uint8_t     DisplayWatermark;
	uint8_t     DeepSleepDivId;
	uint8_t     padding;
	uint32_t    CgSpllFuncCntl;
	uint32_t    CgSpllFuncCntl2;
	uint32_t    CgSpllFuncCntl3;
	uint32_t    CgSpllFuncCntl4;
	uint32_t    SpllSpreadSpectrum;
	uint32_t    SpllSpreadSpectrum2;
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;
};

typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;

struct SMU72_Discrete_Ulv {
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;
	uint16_t    VddcOffset;
	uint8_t     VddcOffsetVid;
	uint8_t     VddcPhase;
	uint32_t    Reserved;
};

typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;

struct SMU72_Discrete_MemoryLevel {
	SMU_VoltageLevel MinVoltage;
	uint32_t    MinMvdd;

	uint32_t    MclkFrequency;

	uint8_t     EdcReadEnable;
	uint8_t     EdcWriteEnable;
	uint8_t     RttEnable;
	uint8_t     StutterEnable;

	uint8_t     StrobeEnable;
	uint8_t     StrobeRatio;
	uint8_t     EnabledForThrottle;
	uint8_t     EnabledForActivity;

	uint8_t     UpHyst;
	uint8_t     DownHyst;

Annotation

Implementation Notes