drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/smu73.h
Extension
.h
Size
19806 bytes
Lines
710
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct SMU7_Poly3rdOrder_Data {
    int32_t a;
    int32_t b;
    int32_t c;
    int32_t d;
    uint8_t a_shift;
    uint8_t b_shift;
    uint8_t c_shift;
    uint8_t x_shift;
};

typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;

struct Power_Calculator_Data {
  uint16_t NoLoadVoltage;
  uint16_t LoadVoltage;
  uint16_t Resistance;
  uint16_t Temperature;
  uint16_t BaseLeakage;
  uint16_t LkgTempScalar;
  uint16_t LkgVoltScalar;
  uint16_t LkgAreaScalar;
  uint16_t LkgPower;
  uint16_t DynVoltScalar;
  uint32_t Cac;
  uint32_t DynPower;
  uint32_t TotalCurrent;
  uint32_t TotalPower;
};

typedef struct Power_Calculator_Data PowerCalculatorData_t;

struct Gc_Cac_Weight_Data {
  uint8_t index;
  uint32_t value;
};

typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;


typedef struct {
  uint32_t high;
  uint32_t low;
} data_64_t;

typedef struct {
  data_64_t high;
  data_64_t low;
} data_128_t;

#define SMU__NUM_SCLK_DPM_STATE  8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8

#define SMU7_CONTEXT_ID_SMC        1
#define SMU7_CONTEXT_ID_VBIOS      2

#define SMU73_MAX_LEVELS_VDDC            16
#define SMU73_MAX_LEVELS_VDDGFX          16
#define SMU73_MAX_LEVELS_VDDCI           8
#define SMU73_MAX_LEVELS_MVDD            4

#define SMU_MAX_SMIO_LEVELS              4

#define SMU73_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
#define SMU73_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
#define SMU73_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
#define SMU73_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
#define SMU73_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
#define SMU73_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
#define SMU73_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
#define SMU73_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
#define SMU73_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.

#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3

#define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
#define SMU7_FIRST_DPM_MEMORY_LEVEL      0

#define GPIO_CLAMP_MODE_VRHOT      1
#define GPIO_CLAMP_MODE_THERM      2
#define GPIO_CLAMP_MODE_DC         4

#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3

Annotation

Implementation Notes