drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h
Extension
.h
Size
24346 bytes
Lines
887
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sclkFcwRange_t {
	uint8_t  vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
	uint8_t  postdiv;     /* divide by 2^n */
	uint16_t fcw_pcc;
	uint16_t fcw_trans_upper;
	uint16_t fcw_trans_lower;
};
typedef struct sclkFcwRange_t sclkFcwRange_t;

struct SMIO_Pattern {
	uint16_t Voltage;
	uint8_t  Smio;
	uint8_t  padding;
};

typedef struct SMIO_Pattern SMIO_Pattern;

struct SMIO_Table {
	SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};

typedef struct SMIO_Table SMIO_Table;

struct SMU_SclkSetting {
	uint32_t    SclkFrequency;
	uint16_t    Fcw_int;
	uint16_t    Fcw_frac;
	uint16_t    Pcc_fcw_int;
	uint8_t     PllRange;
	uint8_t     SSc_En;
	uint16_t    Sclk_slew_rate;
	uint16_t    Pcc_up_slew_rate;
	uint16_t    Pcc_down_slew_rate;
	uint16_t    Fcw1_int;
	uint16_t    Fcw1_frac;
	uint16_t    Sclk_ss_slew_rate;
};
typedef struct SMU_SclkSetting SMU_SclkSetting;

struct SMU75_Discrete_GraphicsLevel {
	SMU_VoltageLevel MinVoltage;

	uint8_t     pcieDpmLevel;
	uint8_t     DeepSleepDivId;
	uint16_t    ActivityLevel;

	uint32_t    CgSpllFuncCntl3;
	uint32_t    CgSpllFuncCntl4;
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;

	uint8_t     SclkDid;
	uint8_t     padding;
	uint8_t     EnabledForActivity;
	uint8_t     EnabledForThrottle;
	uint8_t     UpHyst;
	uint8_t     DownHyst;
	uint8_t     VoltageDownHyst;
	uint8_t     PowerThrottle;

	SMU_SclkSetting SclkSetting;

	uint8_t  ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
	uint16_t Padding;
};

typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel;

struct SMU75_Discrete_ACPILevel {
	uint32_t    Flags;
	SMU_VoltageLevel MinVoltage;
	uint32_t    SclkFrequency;
	uint8_t     SclkDid;
	uint8_t     DisplayWatermark;
	uint8_t     DeepSleepDivId;
	uint8_t     padding;
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;

	SMU_SclkSetting SclkSetting;
};

typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel;

struct SMU75_Discrete_Ulv {
	uint32_t    CcPwrDynRm;
	uint32_t    CcPwrDynRm1;
	uint16_t    VddcOffset;
	uint8_t     VddcOffsetVid;
	uint8_t     VddcPhase;

Annotation

Implementation Notes