drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
Extension
.h
Size
15105 bytes
Lines
489
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef SMU9_DRIVER_IF_H
#define SMU9_DRIVER_IF_H

#include "smu9.h"

/**** IMPORTANT ***
 * SMU TEAM: Always increment the interface version if
 * any structure is changed in this file
 */
#define SMU9_DRIVER_IF_VERSION 0xE

#define PPTABLE_V10_SMU_VERSION 1

#define NUM_GFXCLK_DPM_LEVELS  8
#define NUM_UVD_DPM_LEVELS     8
#define NUM_VCE_DPM_LEVELS     8
#define NUM_MP0CLK_DPM_LEVELS  8
#define NUM_UCLK_DPM_LEVELS    4
#define NUM_SOCCLK_DPM_LEVELS  8
#define NUM_DCEFCLK_DPM_LEVELS 8
#define NUM_LINK_LEVELS        2

#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
#define MAX_UVD_DPM_LEVEL     (NUM_UVD_DPM_LEVELS     - 1)
#define MAX_VCE_DPM_LEVEL     (NUM_VCE_DPM_LEVELS     - 1)
#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
#define MAX_LINK_DPM_LEVEL    (NUM_LINK_LEVELS        - 1)

#define MIN_GFXCLK_DPM_LEVEL  0
#define MIN_UVD_DPM_LEVEL     0
#define MIN_VCE_DPM_LEVEL     0
#define MIN_MP0CLK_DPM_LEVEL  0
#define MIN_UCLK_DPM_LEVEL    0
#define MIN_SOCCLK_DPM_LEVEL  0
#define MIN_DCEFCLK_DPM_LEVEL 0
#define MIN_LINK_DPM_LEVEL    0

#define NUM_EVV_VOLTAGE_LEVELS 8
#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
#define MIN_EVV_VOLTAGE_LEVEL 0

#define NUM_PSP_LEVEL_MAP 4

/* Gemini Modes */
#define PPSMC_GeminiModeNone   0  /* Single GPU board */
#define PPSMC_GeminiModeMaster 1  /* Master GPU on a Gemini board */
#define PPSMC_GeminiModeSlave  2  /* Slave GPU on a Gemini board */

/* Voltage Modes for DPMs */
#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
#define VOLTAGE_MODE_AVFS_WORST_CASE  1
#define VOLTAGE_MODE_STATIC           2

typedef struct {
  uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
  uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
  uint16_t SsSlewFrac;
  uint8_t  SsOn;
  uint8_t  Did;      /* DID */
} PllSetting_t;

typedef struct {
  int32_t a0;
  int32_t a1;
  int32_t a2;

  uint8_t a0_shift;
  uint8_t a1_shift;
  uint8_t a2_shift;
  uint8_t padding;
} GbVdroopTable_t;

typedef struct {
  int32_t m1;
  int32_t m2;
  int32_t b;

  uint8_t m1_shift;
  uint8_t m2_shift;
  uint8_t b_shift;
  uint8_t padding;
} QuadraticInt_t;

#define NUM_DSPCLK_LEVELS 8

typedef enum {
  DSPCLK_DCEFCLK = 0,

Annotation

Implementation Notes