drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.h

Extension

.h

Size

1576 bytes

Lines

51

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• rv_ppsmc.h
• smu10_driver_if.h

Detected Declarations

• struct smu_table_entry
• struct smu_table_array
• struct smu10_smumgr

Annotated Snippet

struct smu_table_entry {
	uint32_t version;
	uint32_t size;
	uint32_t table_id;
	uint64_t mc_addr;
	void *table;
	struct amdgpu_bo *handle;
};

struct smu_table_array {
	struct smu_table_entry entry[MAX_SMU_TABLE];
};

struct smu10_smumgr {
	struct smu_table_array            smu_tables;
};


#endif

Annotation

• Immediate include surface: `rv_ppsmc.h`, `smu10_driver_if.h`.
• Detected declarations: `struct smu_table_entry`, `struct smu_table_array`, `struct smu10_smumgr`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.