drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_8.h
Extension
.h
Size
8485 bytes
Lines
296
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef SMU_15_0_8_DRIVER_IF_H
#define SMU_15_0_8_DRIVER_IF_H

//I2C Interface
#define NUM_I2C_CONTROLLERS                8
#define I2C_CONTROLLER_ENABLED             1
#define I2C_CONTROLLER_DISABLED            0

#define MAX_SW_I2C_COMMANDS                24

typedef enum {
	I2C_CONTROLLER_PORT_0,
	I2C_CONTROLLER_PORT_COUNT,
} I2cControllerPort_e;

typedef enum {
	/* 50  Kbits/s not supported anymore! */
	UNSUPPORTED_1,
	/* 100 Kbits/s */
	I2C_SPEED_STANDARD_100K,
	/* 400 Kbits/s */
	I2C_SPEED_FAST_400K,
	/* 1   Mbits/s (in fast mode) */
	I2C_SPEED_FAST_PLUS_1M,
	/* 1   Mbits/s (in high speed mode)  not supported anymore!*/
	UNSUPPORTED_2,
	/* 2.3 Mbits/s  not supported anymore! */
	UNSUPPORTED_3,
	I2C_SPEED_COUNT,
} I2cSpeed_e;

typedef enum {
	I2C_CMD_READ,
	I2C_CMD_WRITE,
	I2C_CMD_COUNT,
} I2cCmdType_e;

#define CMDCONFIG_STOP_BIT             0
#define CMDCONFIG_RESTART_BIT          1
/* bit should be 0 for read, 1 for write */
#define CMDCONFIG_READWRITE_BIT        2

#define CMDCONFIG_STOP_MASK           (1 << CMDCONFIG_STOP_BIT)
#define CMDCONFIG_RESTART_MASK        (1 << CMDCONFIG_RESTART_BIT)
#define CMDCONFIG_READWRITE_MASK      (1 << CMDCONFIG_READWRITE_BIT)

/* 64 Bit register offsets for PPSMC_MSG_McaBankDumpDW, PPSMC_MSG_McaBankCeDumpDW messages
 * eg to read MCA_BANK_OFFSET_SYND for CE index, call PPSMC_MSG_McaBankCeDumpDW twice,
 * (index << 16 + MCA_BANK_OFFSET_SYND*8) argument for 1st DWORD, and
 * ((index << 16 ) + MCA_BANK_OFFSET_SYND*8 + 4) argument for 2nd DWORD */
typedef enum {
	MCA_BANK_OFFSET_CTL 		= 0,
	MCA_BANK_OFFSET_STATUS 		= 1,
	MCA_BANK_OFFSET_ADDR 		= 2,
	MCA_BANK_OFFSET_MISC 		= 3,
	MCA_BANK_OFFSET_IPID 		= 5,
	MCA_BANK_OFFSET_SYND 		= 6,
	MCA_BANK_OFFSET_MAX 		= 16,
} MCA_BANK_OFFSET_e;

/* Firmware MP1 AID MCA Error Codes stored in MCA_MP_MP1:MCMP1_SYNDT0 errorinformation */
typedef enum {
	/* MMHUB */
	CODE_DAGB0        = 0,
	CODE_DAGB1        = 1,
	CODE_DAGB2        = 2,
	CODE_DAGB3        = 3,
	CODE_DAGB4        = 4,
	CODE_EA0          = 5,
	CODE_EA1          = 6,
	CODE_EA2          = 7,
	CODE_EA3          = 8,
	CODE_EA4          = 9,
	CODE_UTCL2_ROUTER = 10,
	CODE_VML2         = 11,
	CODE_VML2_WALKER  = 12,
	CODE_MMCANE       = 13,

	/* VCN VCPU */
	CODE_VIDD         = 14,
	CODE_VIDV         = 15,
	/* VCN JPEG */
	CODE_JPEG0S       = 16,
	CODE_JPEG0D       = 17,
	CODE_JPEG1S       = 18,
	CODE_JPEG1D       = 19,
	CODE_JPEG2S       = 20,
	CODE_JPEG2D       = 21,
	CODE_JPEG3S       = 22,
	CODE_JPEG3D       = 23,

Annotation

Implementation Notes