drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
Extension: .h
Size: 11097 bytes
Lines: 200
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct smu_11_0_7_overdrive_table
struct smu_11_0_7_power_saving_clock_table
struct smu_11_0_7_powerplay_table
enum SMU_11_0_7_ODFEATURE_CAP
enum SMU_11_0_7_ODFEATURE_ID
enum SMU_11_0_7_ODSETTING_ID
enum SMU_11_0_7_PWRMODE_SETTING
enum SMU_11_0_7_PPCLOCK_ID

Annotated Snippet

#ifndef SMU_11_0_7_PPTABLE_H
#define SMU_11_0_7_PPTABLE_H

#pragma pack(push, 1)

#define SMU_11_0_7_TABLE_FORMAT_REVISION                  15

//// POWERPLAYTABLE::ulPlatformCaps
#define SMU_11_0_7_PP_PLATFORM_CAP_POWERPLAY              0x1            // This cap indicates whether CCC need to show Powerplay page.
#define SMU_11_0_7_PP_PLATFORM_CAP_SBIOSPOWERSOURCE       0x2            // This cap indicates whether power source notificaiton is done by SBIOS instead of OS.
#define SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC             0x4            // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
#define SMU_11_0_7_PP_PLATFORM_CAP_BACO                   0x8            // This cap indicates whether board supports the BACO circuitry.
#define SMU_11_0_7_PP_PLATFORM_CAP_MACO                   0x10           // This cap indicates whether board supports the MACO circuitry.
#define SMU_11_0_7_PP_PLATFORM_CAP_SHADOWPSTATE           0x20           // This cap indicates whether board supports the Shadow Pstate.

// SMU_11_0_7_PP_THERMALCONTROLLER - Thermal Controller Type
#define SMU_11_0_7_PP_THERMALCONTROLLER_NONE              0
#define SMU_11_0_7_PP_THERMALCONTROLLER_SIENNA_CICHLID    28

#define SMU_11_0_7_PP_OVERDRIVE_VERSION                   0x81           // OverDrive 8 Table Version 0.2
#define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION            0x01           // Power Saving Clock Table Version 1.00

enum SMU_11_0_7_ODFEATURE_CAP {
    SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0, 
    SMU_11_0_7_ODCAP_GFXCLK_CURVE,    
    SMU_11_0_7_ODCAP_UCLK_LIMITS,           
    SMU_11_0_7_ODCAP_POWER_LIMIT,        
    SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,   
    SMU_11_0_7_ODCAP_FAN_SPEED_MIN,       
    SMU_11_0_7_ODCAP_TEMPERATURE_FAN,     
    SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,  
    SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,  
    SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, 
    SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,   
    SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,     
    SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,     
    SMU_11_0_7_ODCAP_FAN_CURVE,
    SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
    SMU_11_0_7_ODCAP_POWER_MODE,          
    SMU_11_0_7_ODCAP_COUNT,             
};

enum SMU_11_0_7_ODFEATURE_ID {
    SMU_11_0_7_ODFEATURE_GFXCLK_LIMITS         = 1 << SMU_11_0_7_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
    SMU_11_0_7_ODFEATURE_GFXCLK_CURVE          = 1 << SMU_11_0_7_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
    SMU_11_0_7_ODFEATURE_UCLK_LIMITS           = 1 << SMU_11_0_7_ODCAP_UCLK_LIMITS,              //UCLK Limit feature
    SMU_11_0_7_ODFEATURE_POWER_LIMIT           = 1 << SMU_11_0_7_ODCAP_POWER_LIMIT,              //Power Limit feature
    SMU_11_0_7_ODFEATURE_FAN_ACOUSTIC_LIMIT    = 1 << SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
    SMU_11_0_7_ODFEATURE_FAN_SPEED_MIN         = 1 << SMU_11_0_7_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
    SMU_11_0_7_ODFEATURE_TEMPERATURE_FAN       = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature Limit feature
    SMU_11_0_7_ODFEATURE_TEMPERATURE_SYSTEM    = 1 << SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature Limit feature
    SMU_11_0_7_ODFEATURE_MEMORY_TIMING_TUNE    = 1 << SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
    SMU_11_0_7_ODFEATURE_FAN_ZERO_RPM_CONTROL  = 1 << SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
    SMU_11_0_7_ODFEATURE_AUTO_UV_ENGINE        = 1 << SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK feature
    SMU_11_0_7_ODFEATURE_AUTO_OC_ENGINE        = 1 << SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK feature
    SMU_11_0_7_ODFEATURE_AUTO_OC_MEMORY        = 1 << SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK feature
    SMU_11_0_7_ODFEATURE_FAN_CURVE             = 1 << SMU_11_0_7_ODCAP_FAN_CURVE,                //Fan Curve feature
    SMU_11_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,  //Auto Fan Acoustic RPM feature
    SMU_11_0_7_ODFEATURE_POWER_MODE            = 1 << SMU_11_0_7_ODCAP_POWER_MODE,               //Optimized GPU Power Mode feature
    SMU_11_0_7_ODFEATURE_COUNT                 = 16,
};

#define SMU_11_0_7_MAX_ODFEATURE    32          //Maximum Number of OD Features

enum SMU_11_0_7_ODSETTING_ID {
    SMU_11_0_7_ODSETTING_GFXCLKFMAX = 0,
    SMU_11_0_7_ODSETTING_GFXCLKFMIN,
    SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_A,
    SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_B,
    SMU_11_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_C,
    SMU_11_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMIN,
    SMU_11_0_7_ODSETTING_UCLKFMIN,
    SMU_11_0_7_ODSETTING_UCLKFMAX,
    SMU_11_0_7_ODSETTING_POWERPERCENTAGE,
    SMU_11_0_7_ODSETTING_FANRPMMIN,
    SMU_11_0_7_ODSETTING_FANRPMACOUSTICLIMIT,
    SMU_11_0_7_ODSETTING_FANTARGETTEMPERATURE,
    SMU_11_0_7_ODSETTING_OPERATINGTEMPMAX,
    SMU_11_0_7_ODSETTING_ACTIMING,
    SMU_11_0_7_ODSETTING_FAN_ZERO_RPM_CONTROL,
    SMU_11_0_7_ODSETTING_AUTOUVENGINE,
    SMU_11_0_7_ODSETTING_AUTOOCENGINE,
    SMU_11_0_7_ODSETTING_AUTOOCMEMORY,
    SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_1,
    SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_1,
    SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_2,
    SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_2,
    SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_3,
    SMU_11_0_7_ODSETTING_FAN_CURVE_SPEED_3,
    SMU_11_0_7_ODSETTING_FAN_CURVE_TEMPERATURE_4,

Annotation

Detected declarations: `struct smu_11_0_7_overdrive_table`, `struct smu_11_0_7_power_saving_clock_table`, `struct smu_11_0_7_powerplay_table`, `enum SMU_11_0_7_ODFEATURE_CAP`, `enum SMU_11_0_7_ODFEATURE_ID`, `enum SMU_11_0_7_ODSETTING_ID`, `enum SMU_11_0_7_PWRMODE_SETTING`, `enum SMU_11_0_7_PPCLOCK_ID`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.