drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
Extension
.h
Size
8237 bytes
Lines
168
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct smu_11_0_overdrive_table {
    uint8_t  revision;                                        //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
    uint8_t  reserve[3];                                      //Zero filled field reserved for future use
    uint32_t feature_count;                                   //Total number of supported features
    uint32_t setting_count;                                   //Total number of supported settings
    uint8_t  cap[SMU_11_0_MAX_ODFEATURE];                     //OD feature support flags
    uint32_t max[SMU_11_0_MAX_ODSETTING];                     //default maximum settings
    uint32_t min[SMU_11_0_MAX_ODSETTING];                     //default minimum settings
};

enum SMU_11_0_PPCLOCK_ID {
    SMU_11_0_PPCLOCK_GFXCLK = 0,
    SMU_11_0_PPCLOCK_VCLK,
    SMU_11_0_PPCLOCK_DCLK,
    SMU_11_0_PPCLOCK_ECLK,
    SMU_11_0_PPCLOCK_SOCCLK,
    SMU_11_0_PPCLOCK_UCLK,
    SMU_11_0_PPCLOCK_DCEFCLK,
    SMU_11_0_PPCLOCK_DISPCLK,
    SMU_11_0_PPCLOCK_PIXCLK,
    SMU_11_0_PPCLOCK_PHYCLK,
    SMU_11_0_PPCLOCK_COUNT,
};
#define SMU_11_0_MAX_PPCLOCK      16          //Maximum Number of PP Clocks

struct smu_11_0_power_saving_clock_table {
    uint8_t  revision;                                        //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
    uint8_t  reserve[3];                                      //Zero filled field reserved for future use
    uint32_t count;                                           //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
    uint32_t max[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Maximum array In MHz
    uint32_t min[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Minimum array In MHz
};

struct smu_11_0_powerplay_table {
      struct atom_common_table_header header;
      uint8_t  table_revision;
      uint16_t table_size;                          //Driver portion table size. The offset to smc_pptable including header size
      uint32_t golden_pp_id;
      uint32_t golden_revision;
      uint16_t format_id;
      uint32_t platform_caps;                       //POWERPLAYABLE::ulPlatformCaps

      uint8_t  thermal_controller_type;             //one of SMU_11_0_PP_THERMALCONTROLLER

      uint16_t small_power_limit1;
      uint16_t small_power_limit2;
      uint16_t boost_power_limit;
      uint16_t od_turbo_power_limit;                //Power limit setting for Turbo mode in Performance UI Tuning.
      uint16_t od_power_save_power_limit;           //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
      uint16_t software_shutdown_temp;

      uint16_t reserve[6];                          //Zero filled field reserved for future use

      struct smu_11_0_power_saving_clock_table      power_saving_clock;
      struct smu_11_0_overdrive_table               overdrive_table;

#ifndef SMU_11_0_PARTIAL_PPTABLE
      PPTable_t smc_pptable;                        //PPTable_t in smu11_driver_if.h
#endif
};

#pragma pack(pop)

#endif

Annotation

Implementation Notes