drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
Extension
.c
Size
38888 bytes
Lines
1547
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (args->num_args > 0) {
			for (i = 0; i < args->num_args; i++)
				in[i] = RREG32(ctl->config.arg_regs[i]);
			print_hex_dump(KERN_ERR, "in params:", DUMP_PREFIX_NONE,
				       16, 4, in, args->num_args * sizeof(u32),
				       false);
		}
	}
}

static void __smu_msg_v1_print_error(struct smu_msg_ctl *ctl,
				     u32 resp,
				     struct smu_msg_args *args)
{
	struct smu_context *smu = ctl->smu;
	struct amdgpu_device *adev = smu->adev;
	int index = ctl->message_map[args->msg].map_to;

	switch (resp) {
	case SMU_RESP_NONE:
		__smu_msg_v1_print_err_limited(ctl, args, "SMU: No response");
		break;
	case SMU_RESP_OK:
		break;
	case SMU_RESP_CMD_FAIL:
		break;
	case SMU_RESP_CMD_UNKNOWN:
		__smu_msg_v1_print_err_limited(ctl, args,
					       "SMU: unknown command");
		break;
	case SMU_RESP_CMD_BAD_PREREQ:
		__smu_msg_v1_print_err_limited(
			ctl, args, "SMU: valid command, bad prerequisites");
		break;
	case SMU_RESP_BUSY_OTHER:
		if (args->msg != SMU_MSG_GetBadPageCount)
			__smu_msg_v1_print_err_limited(ctl, args,
						       "SMU: I'm very busy");
		break;
	case SMU_RESP_DEBUG_END:
		__smu_msg_v1_print_err_limited(ctl, args, "SMU: Debug Err");
		break;
	case SMU_RESP_UNEXP:
		if (amdgpu_device_bus_status_check(adev)) {
			dev_err(adev->dev,
				"SMU: bus error for message: %s(%d) response:0x%08X ",
				smu_get_message_name(smu, args->msg), index,
				resp);
			if (args->num_args > 0)
				print_hex_dump(KERN_ERR,
					       "in params:", DUMP_PREFIX_NONE,
					       16, 4, args->args,
					       args->num_args * sizeof(u32),
					       false);
		}
		break;
	default:
		__smu_msg_v1_print_err_limited(ctl, args,
					       "SMU: unknown response");
		break;
	}
}

static int __smu_msg_v1_ras_filter(struct smu_msg_ctl *ctl,
				   enum smu_message_type msg, u32 msg_flags,
				   bool *skip_pre_poll)
{
	struct smu_context *smu = ctl->smu;
	struct amdgpu_device *adev = smu->adev;
	bool fed_status;
	u32 reg;

	if (!(smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI))
		return 0;

	fed_status = amdgpu_ras_get_fed_status(adev);

	/* Block non-RAS-priority messages during RAS error */
	if (fed_status && !(msg_flags & SMU_MSG_RAS_PRI)) {
		dev_dbg(adev->dev, "RAS error detected, skip sending %s",
			smu_get_message_name(smu, msg));
		return -EACCES;
	}

	/* Skip pre-poll for priority messages or during RAS error */
	if ((msg_flags & SMU_MSG_NO_PRECHECK) || fed_status) {
		reg = RREG32(ctl->config.resp_reg);
		dev_dbg(adev->dev,
			"Sending priority message %s response status: %x",
			smu_get_message_name(smu, msg), reg);

Annotation

Implementation Notes