drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c- Extension
.c- Size
- 11689 bytes
- Lines
- 388
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_smu.hatomfirmware.hamdgpu_atomfirmware.hamdgpu_atombios.hsmu_v12_0.hsoc15_common.hatom.hsmu_cmn.hasic_reg/mp/mp_12_0_0_offset.hasic_reg/mp/mp_12_0_0_sh_mask.hasic_reg/smuio/smuio_12_0_0_offset.hasic_reg/smuio/smuio_12_0_0_sh_mask.h
Detected Declarations
function filesfunction smu_v12_0_powergate_sdmafunction smu_v12_0_set_gfx_cgpgfunction smu_v12_0_get_gfxoff_statusfunction smu_v12_0_gfx_off_controlfunction smu_v12_0_fini_smc_tablesfunction smu_v12_0_set_default_dpm_tablesfunction smu_v12_0_mode2_resetfunction smu_v12_0_set_soft_freq_limited_rangefunction smu_v12_0_set_driver_table_locationfunction smu_v12_0_atom_get_smu_clockinfofunction smu_v12_0_get_vbios_bootup_valuesfunction smu_v12_0_init_msg_ctl
Annotated Snippet
while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
msleep(1);
timeout--;
if (timeout == 0) {
DRM_ERROR("disable gfxoff timeout and failed!\n");
break;
}
}
}
return ret;
}
int smu_v12_0_fini_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
kfree(smu_table->clocks_table);
smu_table->clocks_table = NULL;
kfree(smu_table->metrics_table);
smu_table->metrics_table = NULL;
kfree(smu_table->watermarks_table);
smu_table->watermarks_table = NULL;
smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
return 0;
}
int smu_v12_0_set_default_dpm_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
}
int smu_v12_0_mode2_reset(struct smu_context *smu)
{
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
}
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max, bool automatic)
{
int ret = 0;
if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
return 0;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min, NULL);
if (ret)
return ret;
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max, NULL);
if (ret)
return ret;
break;
case SMU_FCLK:
case SMU_MCLK:
case SMU_UCLK:
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
if (ret)
return ret;
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max, NULL);
if (ret)
return ret;
break;
case SMU_SOCCLK:
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min, NULL);
if (ret)
return ret;
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max, NULL);
if (ret)
return ret;
break;
case SMU_VCLK:
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min, NULL);
if (ret)
return ret;
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max, NULL);
if (ret)
return ret;
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_smu.h`, `atomfirmware.h`, `amdgpu_atomfirmware.h`, `amdgpu_atombios.h`, `smu_v12_0.h`, `soc15_common.h`.
- Detected declarations: `function files`, `function smu_v12_0_powergate_sdma`, `function smu_v12_0_set_gfx_cgpg`, `function smu_v12_0_get_gfxoff_status`, `function smu_v12_0_gfx_off_control`, `function smu_v12_0_fini_smc_tables`, `function smu_v12_0_set_default_dpm_tables`, `function smu_v12_0_mode2_reset`, `function smu_v12_0_set_soft_freq_limited_range`, `function smu_v12_0_set_driver_table_location`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.