drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c- Extension
.c- Size
- 120976 bytes
- Lines
- 4027
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_smu.hatomfirmware.hamdgpu_atomfirmware.hamdgpu_atombios.hsmu_v13_0_6_pmfw.hsmu13_driver_if_v13_0_6.hsmu_v13_0_6_ppsmc.hsoc15_common.hatom.hpower_state.hsmu_v13_0.hsmu_v13_0_6_ppt.hnbio/nbio_7_4_offset.hnbio/nbio_7_4_sh_mask.hthm/thm_11_0_2_offset.hthm/thm_11_0_2_sh_mask.hamdgpu_xgmi.hlinux/pci.hamdgpu_ras.hamdgpu_mca.hamdgpu_aca.hsmu_cmn.hmp/mp_13_0_6_offset.hmp/mp_13_0_6_sh_mask.humc_v12_0.h
Detected Declarations
struct mca_bank_ipidstruct mca_ras_infostruct smu_v13_0_6_dpm_mapfunction smu_v13_0_6_get_metrics_versionfunction smu_v13_0_6_cap_setfunction smu_v13_0_6_cap_clearfunction smu_v13_0_6_cap_supportedfunction smu_v13_0_14_init_capsfunction smu_v13_0_12_init_capsfunction smu_v13_0_6_init_capsfunction smu_v13_0_x_init_capsfunction smu_v13_0_6_check_fw_versionfunction smu_v13_0_6_init_microcodefunction smu_v13_0_6_tables_initfunction IP_VERSIONfunction smu_v13_0_6_select_policy_soc_pstatefunction smu_v13_0_6_select_plpd_policyfunction smu_v13_0_6_allocate_dpm_contextfunction smu_v13_0_6_init_smc_tablesfunction smu_v13_0_6_fini_smc_tablesfunction smu_v13_0_6_init_allowed_featuresfunction smu_v13_0_6_get_metrics_tablefunction smu_v13_0_6_get_pm_metricsfunction smu_v13_0_6_fill_static_metrics_tablefunction smu_v13_0_6_get_static_metrics_tablefunction smu_v13_0_6_update_capsfunction smu_v13_0_6_setup_driver_pptablefunction smu_v13_0_6_get_dpm_ultimate_freqfunction smu_v13_0_6_get_dpm_level_countfunction smu_v13_0_6_pm_policy_initfunction smu_v13_0_6_set_default_dpm_tablefunction smu_v13_0_6_setup_pptablefunction smu_v13_0_6_check_fw_statusfunction smu_v13_0_6_populate_umd_state_clkfunction smu_v13_0_6_get_throttler_statusfunction smu_v13_0_6_get_smu_metrics_datafunction smu_v13_0_6_get_current_clk_freq_by_tablefunction smu_v13_0_6_emit_clk_levelsfunction smu_v13_0_6_upload_dpm_levelfunction smu_v13_0_6_force_clk_levelsfunction smu_v13_0_6_get_current_activity_percentfunction smu_v13_0_6_thermal_get_temperaturefunction smu_v13_0_6_read_sensorfunction smu_v13_0_6_get_power_limitfunction smu_v13_0_6_set_power_limitfunction smu_v13_0_6_get_ppt_limitfunction smu_v13_0_6_irq_processfunction smu_v13_0_6_set_irq_state
Annotated Snippet
struct mca_bank_ipid {
enum amdgpu_mca_ip ip;
uint16_t hwid;
uint16_t mcatype;
};
struct mca_ras_info {
enum amdgpu_ras_block blkid;
enum amdgpu_mca_ip ip;
int *err_code_array;
int err_code_count;
int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
};
#define P2S_TABLE_ID_A 0x50325341
#define P2S_TABLE_ID_X 0x50325358
#define P2S_TABLE_ID_3 0x50325303
// clang-format off
static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1),
MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),
MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1),
};
// clang-format on
static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(SOCCLK, PPCLK_SOCCLK),
CLK_MAP(FCLK, PPCLK_FCLK),
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(DCLK, PPCLK_DCLK),
CLK_MAP(VCLK, PPCLK_VCLK),
CLK_MAP(LCLK, PPCLK_LCLK),
};
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_smu.h`, `atomfirmware.h`, `amdgpu_atomfirmware.h`, `amdgpu_atombios.h`, `smu_v13_0_6_pmfw.h`, `smu13_driver_if_v13_0_6.h`.
- Detected declarations: `struct mca_bank_ipid`, `struct mca_ras_info`, `struct smu_v13_0_6_dpm_map`, `function smu_v13_0_6_get_metrics_version`, `function smu_v13_0_6_cap_set`, `function smu_v13_0_6_cap_clear`, `function smu_v13_0_6_cap_supported`, `function smu_v13_0_14_init_caps`, `function smu_v13_0_12_init_caps`, `function smu_v13_0_6_init_caps`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.