drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
Extension: .h
Size: 20961 bytes
Lines: 348
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

smu_cmn.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __SMU_15_0_8_PPT_H__
#define __SMU_15_0_8_PPT_H__

#define SMU_15_0_8_NUM_XGMI_LINKS 8
#define SMU_15_0_8_MAX_GFX_CLKS 8
#define SMU_15_0_8_MAX_CLKS 4
#define SMU_15_0_8_MAX_XCC 8
#define SMU_15_0_8_MAX_VCN 4
#define SMU_15_0_8_MAX_JPEG 40
#define SMU_15_0_8_MAX_AID 2
#define SMU_15_0_8_MAX_MID 2
#define SMU_15_0_8_MAX_HBM_STACKS 12
extern void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu);

typedef struct {
	uint32_t MaxSocketPowerLimit;
	uint32_t MaxGfxclkFrequency;
	uint32_t MinGfxclkFrequency;
	uint32_t MaxFclkFrequency;
	uint32_t MinFclkFrequency;
	uint32_t MaxGl2clkFrequency;
	uint32_t MinGl2clkFrequency;
	uint32_t UclkFrequencyTable[4];
	uint32_t SocclkFrequency;
	uint32_t LclkFrequency;
	uint32_t VclkFrequency;
	uint32_t DclkFrequency;
	uint32_t CTFLimitMID;
	uint32_t CTFLimitAID;
	uint32_t CTFLimitXCD;
	uint32_t CTFLimitHBM;
	uint32_t ThermalLimitMID;
	uint32_t ThermalLimitAID;
	uint32_t ThermalLimitXCD;
	uint32_t ThermalLimitHBM;
	uint64_t PublicSerialNumberMID;
	uint64_t PublicSerialNumberAID;
	uint64_t PublicSerialNumberXCD;
	uint32_t PPT1Max;
	uint32_t PPT1Min;
	uint32_t PPT1Default;
	bool init;
} PPTable_t;

#if defined(SWSMU_CODE_LAYER_L2)
#include "smu_cmn.h"

/* SMUv 15.0.8 GPU metrics*/
#define SMU_15_0_8_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY)                       \
	SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1),          \
		   SMU_MTYPE(U16), temperature_hotspot);                       \
	SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1),              \
		   SMU_MTYPE(U16), temperature_mem);                           \
	SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1),            \
		   SMU_MTYPE(U16), temperature_vrsoc);                         \
	SMU_ARRAY(SMU_MATTR(TEMPERATURE_HBM), SMU_MUNIT(TEMP_1),               \
		  SMU_MTYPE(U16), temperature_hbm,                             \
		  SMU_15_0_8_MAX_HBM_STACKS);                                  \
	SMU_ARRAY(SMU_MATTR(TEMPERATURE_MID), SMU_MUNIT(TEMP_1),               \
		  SMU_MTYPE(U16), temperature_mid, SMU_15_0_8_MAX_MID);        \
	SMU_ARRAY(SMU_MATTR(TEMPERATURE_AID), SMU_MUNIT(TEMP_1),               \
		  SMU_MTYPE(U16), temperature_aid, SMU_15_0_8_MAX_AID);        \
	SMU_ARRAY(SMU_MATTR(TEMPERATURE_XCD), SMU_MUNIT(TEMP_1),               \
		  SMU_MTYPE(U16), temperature_xcd, SMU_15_0_8_MAX_XCC);        \
	SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1),           \
		   SMU_MTYPE(U16), curr_socket_power);                         \
	SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT),        \
		   SMU_MTYPE(U16), average_gfx_activity);                      \
	SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT),        \
		   SMU_MTYPE(U16), average_umc_activity);                      \
	SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1),              \
		   SMU_MTYPE(U64), mem_max_bandwidth);                         \
	SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE),             \
		   SMU_MTYPE(U64), energy_accumulator);                        \
	SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1),         \
		   SMU_MTYPE(U64), system_clock_counter);                      \
	SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE),           \
		   SMU_MTYPE(U64), accumulation_counter);                      \
	SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE),          \
		   SMU_MTYPE(U64), prochot_residency_acc);                     \
	SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE),              \
		   SMU_MTYPE(U64), ppt_residency_acc);                         \
	SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE),       \
		   SMU_MTYPE(U64), socket_thm_residency_acc);                  \
	SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE),           \
		   SMU_MTYPE(U64), vr_thm_residency_acc);                      \
	SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE),          \
		   SMU_MTYPE(U64), hbm_thm_residency_acc);                     \
	SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE),             \
		   SMU_MTYPE(U32), gfxclk_lock_status);                        \

Annotation

Immediate include surface: `smu_cmn.h`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.